diff -Nur /home/anderstj/linux-2.4.26/.cvsignore ./.cvsignore --- /home/anderstj/linux-2.4.26/.cvsignore 1970-01-01 01:00:00.000000000 +0100 +++ ./.cvsignore 2001-11-08 15:19:08.000000000 +0100 @@ -0,0 +1,6 @@ +.config +vmlinux +vmlinux.bin +System.map +rescue.bin +decompress.bin diff -Nur /home/anderstj/linux-2.4.26/Documentation/Configure.help ./Documentation/Configure.help --- /home/anderstj/linux-2.4.26/Documentation/Configure.help 2004-04-14 15:05:24.000000000 +0200 +++ ./Documentation/Configure.help 2004-04-19 10:16:21.000000000 +0200 @@ -14567,9 +14567,9 @@ Debugging RAM test driver CONFIG_MTD_MTDRAM - This enables a test MTD device driver which uses vmalloc() to - provide storage. You probably want to say 'N' unless you're - testing stuff. + This enables a test MTD device driver which uses vmalloc() + or an absolute address to provide storage. + You probably want to say 'N' unless you're testing stuff. This driver is also available as a module ( = code which can be inserted in and removed from the running kernel whenever you want). @@ -14590,6 +14590,8 @@ emulated by the MTDRAM driver. If the MTDRAM driver is built as a module, it is also possible to specify this as a parameter when loading the module. + If you want to set the size and position at runtime, set to 0, + in that case set the ABS_POS parameter to 0 as well. SRAM Hexadecimal Absolute position or 0 CONFIG_MTDRAM_ABS_POS @@ -26699,15 +26701,15 @@ you should say N to this option. # Choice: cristype -Etrax-100-LX-v1 +ETRAX-100-LX-v1 CONFIG_ETRAX100LX - Support version 1 of the Etrax 100LX. + Support version 1 of the ETRAX 100LX. -Etrax-100-LX-v2 +ETRAX-100-LX-v2 CONFIG_ETRAX100LX_V2 - Support version 2 of the Etrax 100LX. + Support version 2 of the ETRAX 100LX. -Etrax-100-LX-for-xsim-simulator +ETRAX-100-LX-for-xsim-simulator CONFIG_SVINTO_SIM Support the xsim ETRAX Simulator. @@ -26719,10 +26721,18 @@ CONFIG_ETRAX_FLASH_BUSWIDTH Width in bytes of the Flash bus (1, 2 or 4). Is usually 2. +Root filesystem device +CONFIG_ETRAX_ROOT_DEVICE + Specifies the device that should be mounted as root filesystem + when booting from flash. The axisflashmap driver adds an additional + mtd partition for the appended root filesystem image, so this option + should normally be the mtdblock device for the partition after the + last partition in the partition table. + # Choice: crisleds LED configuration on PA CONFIG_ETRAX_PA_LEDS - The Etrax network driver is responsible for flashing LED's when + The ETRAX network driver is responsible for flashing LED's when packets arrive and are sent. It uses macros defined in , and those macros are defined after what YOU choose in this option. The actual bits used are configured @@ -26731,7 +26741,7 @@ LED configuration on PB CONFIG_ETRAX_PB_LEDS - The Etrax network driver is responsible for flashing LED's when + The ETRAX network driver is responsible for flashing LED's when packets arrive and are sent. It uses macros defined in , and those macros are defined after what YOU choose in this option. The actual bits used are configured @@ -26740,7 +26750,7 @@ LED configuration on CSP0 CONFIG_ETRAX_CSP0_LEDS - The Etrax network driver is responsible for flashing LED's when + The ETRAX network driver is responsible for flashing LED's when packets arrive and are sent. It uses macros defined in , and those macros are defined after what YOU choose in this option. The actual bits used are configured @@ -26868,14 +26878,34 @@ For products with only one or two controllable LEDs, set this to same as CONFIG_ETRAX_LED1G (normally 2). -Flash LED off during activity -CONFIG_ETRAX_LED_OFF_DURING_ACTIVITY - This option allows you to decide whether the network LED (and - Bluetooth LED in case you use Bluetooth) will be on or off when - the network is connected, and whether it should flash off or on - when there is activity. If you say y to this option the network - LED will be lit when there is a connection, and will flash off - when there is activity. +Network LED behavior +CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK + Selecting LED_on_when_link will light the LED when there is a + connection and will flash off when there is activity. + + Selecting LED_on_when_activity will light the LED only when + there is activity. + + This setting will also affect the behaviour of other activity LEDs + e.g. Bluetooth. + +Network LED behavior +CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY + Selecting LED_on_when_link will light the LED when there is a + connection and will flash off when there is activity. + + Selecting LED_on_when_activity will light the LED only when + there is activity. + + This setting will also affect the behaviour of other activity LEDs + e.g. Bluetooth. + +Network LED behavior on no connection +RED_LED_on_no_connection + Will signal a lost network connection by turning network led red. + +LED_OFF_on_no_connection + Network led is turned off when network connection is lost. PA button configuration CONFIG_ETRAX_PA_BUTTON_BITMASK @@ -26885,7 +26915,7 @@ use 02 here. Use 00 if there are no buttons on PA. If the bitmask is <> 00 a button driver will be included in the gpio - driver. Etrax general I/O support must be enabled. + driver. ETRAX general I/O support must be enabled. PA changeable direction bits CONFIG_ETRAX_PA_CHANGEABLE_DIR @@ -26897,7 +26927,7 @@ PA changeable data bits CONFIG_ETRAX_PA_CHANGEABLE_BITS This is a bitmask with information of what bits in PA that a user - can change change the value on using ioctl's. + can change the value on using ioctl's. Bit set = changeable. You probably want 00 here. @@ -26928,17 +26958,29 @@ didn't before). The kernel halts when it boots, waiting for gdb if this option is turned on! -Etrax bus waitstates +ETRAX interrupt debugging +CONFIG_ETRAX_DEBUG_INTERRUPT + This options enables logging of when interrupts are turned on and off. + The log can be seen in /proc/debug_interupt + +ETRAX fast timer API +CONFIG_ETRAX_FAST_TIMER + This options enables the API to a fast timer implementation using + timer1 to get sub jiffie resolution timers (primarily one-shot + timers). + This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled. + +ETRAX bus waitstates CONFIG_ETRAX_DEF_R_WAITSTATES Waitstates for SRAM, Flash and peripherals (not DRAM). 95f8 is a good choice for most Axis products... -Etrax bus configuration +ETRAX bus configuration CONFIG_ETRAX_DEF_R_BUS_CONFIG Assorted bits controlling write mode, DMA burst length etc. 104 is a good choice for most Axis products... -Etrax SDRAM configuration +ETRAX SDRAM configuration CONFIG_ETRAX_SDRAM Enable this if you use SDRAM chips and configure R_SDRAM_CONFIG and R_SDRAM_TIMING as well. @@ -26946,29 +26988,29 @@ DRAM size (dec, in MB) CONFIG_ETRAX_DEF_R_DRAM_CONFIG The R_DRAM_CONFIG register specifies everything on how the DRAM - chips in the system are connected to the Etrax CPU. This is + chips in the system are connected to the ETRAX CPU. This is different depending on the manufacturer, chip type and number of chips. So this value often needs to be different for each Axis product. -Etrax DRAM timing +ETRAX DRAM timing CONFIG_ETRAX_DEF_R_DRAM_TIMING Different DRAM chips have different speeds. Current Axis products use 50ns DRAM chips which can use the timing: 5611. -Etrax SDRAM configuration +ETRAX SDRAM configuration CONFIG_ETRAX_DEF_R_SDRAM_CONFIG The R_SDRAM_CONFIG register specifies everything on how the SDRAM - chips in the system are connected to the Etrax CPU. This is + chips in the system are connected to the ETRAX CPU. This is different depending on the manufacturer, chip type and number of chips. So this value often needs to be different for each Axis product. -Etrax SDRAM timing +ETRAX SDRAM timing CONFIG_ETRAX_DEF_R_SDRAM_TIMING Different SDRAM chips have different timing. -Etrax General port A direction +ETRAX General port A direction CONFIG_ETRAX_DEF_R_PORT_PA_DIR Configures the direction of general port A bits. 1 is out, 0 is in. This is often totally different depending on the product used. @@ -26979,17 +27021,17 @@ stuff. If you don't know what to use, it is always safe to put all as inputs, although floating inputs isn't good. -Etrax General port A data +ETRAX General port A data CONFIG_ETRAX_DEF_R_PORT_PA_DATA Configures the initial data for the general port A bits. Most products should use 00 here. -Etrax General port B config +ETRAX General port B config CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG Configures the type of the general port B bits. 1 is chip select, 0 is port. Most products should use 00 here. -Etrax General port B direction +ETRAX General port B direction CONFIG_ETRAX_DEF_R_PORT_PB_DIR Configures the direction of general port B bits. 1 is out, 0 is in. This is often totally different depending on the product used. Bits @@ -26999,14 +27041,28 @@ If you don't know what to use, it is always safe to put all as inputs. -Etrax General port B data +ETRAX General port B data CONFIG_ETRAX_DEF_R_PORT_PB_DATA - Configures the initial data for the general port A bits. Most + Configures the initial data for the general port B bits. Most products should use FF here. -Etrax General port device +ETRAX shutdown support +CONFIG_ETRAX_SOFT_SHUTDOWN + Enable this if ETRAX is used with a power-supply that can be turned + off and on with PS_ON signal. Gives the possibility to detect + powerbutton and then do a power off after unmounting disks. + +ETRAX shutdown support output +CONFIG_ETRAX_SHUTDOWN_BIT + Configure what pin on CSPO-port that is used for controlling power supply. + +ETRAX shutdown support input +CONFIG_ETRAX_POWERBUTTON_BIT + Configure where power button is connected. + +ETRAX General port device CONFIG_ETRAX_GPIO - Enables the Etrax general port device (major 120, minors 0 and 1). + Enables the ETRAX general port device (major 120, minors 0 and 1). You can use this driver to access the general port bits. It supports these ioctl's: #include @@ -27017,19 +27073,19 @@ Remember that you need to setup the port directions appropriately in the General configuration. -Etrax parallel data support +ETRAX parallel data support CONFIG_ETRAX_PARDATA Adds support for writing data to the parallel port par0 of the ETRAX 100. If you create a character special file with major number 126, you can write to the data bits of par0. - Note: you need to disable Etrax100 parallel port support. + Note: you need to disable ETRAX 100 parallel port support. -Etrax parallel LCD (HD44780) Driver +ETRAX parallel LCD (HD44780) Driver CONFIG_ETRAX_LCD_HD44780 Adds support for a HD44780 controlled LCD connected to the parallel - port par0 of the Etrax. + port par0 of the ETRAX. -Etrax Serial port ser0 support +ETRAX Serial port ser0 support CONFIG_ETRAX_SERIAL Enables the ETRAX 100 serial driver for ser0 (ttyS0) You probably want this enabled. @@ -27039,28 +27095,54 @@ Enables /proc/serial entry where errors and statistics can be viewed. CONFIG_PROC_FS must also be set for this to work. -Etrax Serial port fast flush of DMA using fast timer API +ETRAX Serial port fast flush of DMA using fast timer API CONFIG_ETRAX_SERIAL_FAST_TIMER Select this to have the serial DMAs flushed at a higher rate than normally, possible by using the fast timer API, the timeout is approx. 4 character times. If unsure, say N. -Etrax Serial port fast flush of DMA +ETRAX Serial port fast flush of DMA CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST Select this to have the serial DMAs flushed at a higher rate than normally possible through a fast timer interrupt (currently at 15360 Hz). If unsure, say N. -Etrax Serial port receive flush timeout +ETRAX Serial port receive flush timeout CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS Number of timer ticks between flush of receive fifo (1 tick = 10ms). - Try 0-3 for low latency applications. Approx 5 for high load + Try 1-3 for low latency applications. Approx 5 for high load applications (e.g. PPP). Maybe this should be more adaptive some day... -Etrax Serial port ser0 DTR, RI, DSR and CD support on PB +ETRAX External clock on PB6 +CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED + Select this if you intend to use an external clock on PB6 + for baudrate (or timer0). + +ETRAX External clock on PB6 frequency +CONFIG_ETRAX_EXTERN_PB6CLK_FREQ + The frequency of the external clock supplied on PB6. + If used as a baudrate clock, the baudrate is this clk/8. + +ETRAX Serial port ser0 support +CONFIG_ETRAX_SERIAL_PORT0 + Enables the ETRAX 100 serial driver for ser0 (ttyS0) + Normally you want this on, unless you use external DMA 1 that uses + the same DMA channels. + +ETRAX Serial port ser0 uses DMA6 for output +CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT + ETRAX Serial port ser0 uses DMA6 for output. + External DMA 1 uses this DMA channel as well. + +ETRAX Serial port ser0 uses DMA7 for input +CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN + ETRAX Serial port ser0 uses DMA7 for input. + External DMA 1 uses this DMA channel as well. + +ETRAX Serial port ser0 DTR, RI, DSR and CD support on PB CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB Enables the status and control signals DTR, RI, DSR and CD on PB for ser0. @@ -27069,7 +27151,17 @@ CONFIG_ETRAX_SERIAL_PORT1 Enables the ETRAX 100 serial driver for ser1 (ttyS1). -Etrax Serial port ser1 DTR, RI, DSR and CD support on PB +ETRAX Serial port ser1 uses DMA8 for output +CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT + ETRAX Serial port ser1 uses DMA8 for output. + USB uses this DMA channel as well. + +ETRAX Serial port ser1 uses DMA9 for input +CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN + ETRAX Serial port ser1 uses DMA9 for input. + USB uses this DMA channel as well. + +ETRAX Serial port ser1 DTR, RI, DSR and CD support on PB CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB Enables the status and control signals DTR, RI, DSR and CD on PB for ser1. @@ -27078,7 +27170,18 @@ CONFIG_ETRAX_SERIAL_PORT2 Enables the ETRAX 100 serial driver for ser2 (ttyS2). -Etrax Serial port ser2 DTR, RI, DSR and CD support on PA +ETRAX Serial port ser2 uses DMA2 for output +CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT + ETRAX Serial port ser2 uses DMA2 for output. + par0, scsi0 and ATA uses this DMA channel as well. + +ETRAX Serial port ser2 uses DMA3 for input +CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN + ETRAX Serial port ser2 uses DMA3 for input. + par0, scsi0 and ATA uses this DMA channel as well. + + +ETRAX Serial port ser2 DTR, RI, DSR and CD support on PA CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA Enables the status and control signals DTR, RI, DSR and CD on PA for ser2. @@ -27087,22 +27190,41 @@ CONFIG_ETRAX_SERIAL_PORT3 Enables the ETRAX 100 serial driver for ser3 (ttyS3). -Etrax100 RS-485 support +ETRAX Serial port ser3 uses DMA4 for output +CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT + ETRAX Serial port ser3 uses DMA4 for output. + External DMA 0, par1 and scsi1 uses this DMA channel as well. + +ETRAX Serial port ser3 uses DMA5 for input +CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN + ETRAX Serial port ser3 uses DMA5 for input. + External DMA 0, par1 and scsi1 uses this DMA channel as well. + +ETRAX RS-485 support CONFIG_ETRAX_RS485 Enables support for RS-485 serial communication. For a primer on RS-485, see . -Etrax100 RS-485 mode on PA +ETRAX RS-485 mode on PA CONFIG_ETRAX_RS485_ON_PA Control Driver Output Enable on RS485 transceiver using a pin on PA port: Axis 2400/2401 uses PA 3. -Etrax100 RS-485 mode on PA bit +ETRAX RS-485 mode on PA bit CONFIG_ETRAX_RS485_ON_PA_BIT Control Driver Output Enable on RS485 transceiver using a this bit on PA port. +ETRAX RS-485 mode on G port +CONFIG_ETRAX_RS485_ON_PORT_G + Control Driver Output Enable on RS485 transceiver using a pin on port G + +ETRAX RS-485 mode on port G bit +CONFIG_ETRAX_RS485_ON_PORT_G_BIT + Control Driver Output Enable on RS485 transceiver using this bit + on G port. + Ser0 DTR on PB bit CONFIG_ETRAX_SER0_DTR_ON_PB_BIT Specify the pin of the PB port to carry the DTR signal for serial @@ -27163,22 +27285,33 @@ Specify the pin of the PA port to carry the CD signal for serial port 2. -Etrax100 RS-485 disable receiver +ETRAX RS-485 disable receiver CONFIG_ETRAX_RS485_DISABLE_RECEIVER It's necessary to disable the serial receiver to avoid serial loopback. Not all products are able to do this in software only. Axis 2400/2401 must disable receiver. -Etrax100 I2C Support +ETRAX LTC1387 support +CONFIG_ETRAX_LTC1387 + Enable support for LTC1387 multiprotocol transceiver on serial + port 2. + +CONFIG_ETRAX_LTC1387_DXEN_PORT_G_BIT + Specify the pin of port G for DXEN on the LTC1387 chip. + +CONFIG_ETRAX_LTC1387_RXEN_PORT_G_BIT + Specify the pin of port G for RXEN on the LTC1387 chip. + +ETRAX I2C Support CONFIG_ETRAX_I2C - Enables an I2C driver on PB0 and PB1 on ETRAX100. + Enables an I2C driver on ETRAX. EXAMPLE usage: i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); -Etrax100 I2C configuration +ETRAX I2C configuration CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C Select whether to use the special I2C mode in the PB I/O register or not. This option needs to be selected in order to use some drivers @@ -27186,77 +27319,138 @@ I2C driver, like the DS1302 realtime-clock driver. If you are uncertain, choose Y here. -Etrax100 I2C EEPROM (NVRAM) support +ETRAX I2C data pin configuration +CONFIG_ETRAX_I2C_DATA_PORT + Selects the pin on Port B where the data pin is connected + +ETRAX I2C clock pin configuration +CONFIG_ETRAX_I2C_CLK_PORT + Select the pin on Port B where the clock pin is connected + +ETRAX I2C EEPROM (NVRAM) support CONFIG_ETRAX_I2C_EEPROM Enables I2C EEPROM (non-volatile RAM) on PB0 and PB1 using the I2C driver. Select size option: Probed, 2k, 8k, 16k. (Probing works for 2k and 8k but not that well for 16k) -Etrax100 I2C EEPROM (NVRAM) size/16kB +ETRAX I2C EEPROM (NVRAM) size/16kB CONFIG_ETRAX_I2C_EEPROM_16KB Use a 16kB EEPROM. -Etrax100 I2C EEPROM (NVRAM) size/2kB +ETRAX I2C EEPROM (NVRAM) size/2kB CONFIG_ETRAX_I2C_EEPROM_2KB Use a 2kB EEPROM. -Etrax100 I2C EEPROM (NVRAM) size/8kB +ETRAX I2C EEPROM (NVRAM) size/8kB CONFIG_ETRAX_I2C_EEPROM_8KB Use a 8kB EEPROM. # Choice: etrax_eeprom -Etrax100 I2C EEPROM (NVRAM) size/probe +ETRAX I2C EEPROM (NVRAM) size/probe CONFIG_ETRAX_I2C_EEPROM_PROBE Specifies size or auto probe of the EEPROM size. Options: Probed, 2k, 8k, 16k. (Probing works for 2k and 8k but not that well for 16k) -Etrax DS1302 Real-Time Clock driver -CONFIG_ETRAX_DS1302 - Enables the driver for the DS1302 Real-Time Clock battery-backed - chip on some products. The kernel reads the time when booting, and +ETRAX Port G direction +CONFIG_ETRAX_DEF_R_PORT_G_DIR + Set the direction of specified pins to output. + +ETRAX Port G0 +CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT + Set G0 to output. + +ETRAX Port G8-G15 +CONFIG_ETRAX_DEF_R_PORT_G8_15_DIR_OUT + Set G8-G15 to output. + +ETRAX Port G16-G23 +CONFIG_ETRAX_DEF_R_PORT_G16_23_DIR_OUT + Set G16-G23 to output. + +ETRAX Port G24 +CONFIG_ETRAX_DEF_R_PORT_G24_DIR_OUT + Set G24 to output. + +ETRAX Real-Time Clock drivers +CONFIG_ETRAX_RTC + Enables drivers for the Real-Time Clock battery-backed chips on + some products. The kernel reads the time when booting, and the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a rtc_time struct (see ) on the /dev/rtc device, major 121. You can check the time with cat /proc/rtc, but normal time reading should be done using libc function time and friends. -Etrax DS1302 RST on the Generic Port +ETRAX DS1302 Real-Time Clock driver +CONFIG_ETRAX_DS1302 + Enables the driver for the DS1302 Real-Time Clock battery-backed + chip on some products. + +ETRAX DS1302 RST on the Generic Port CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT If your product has the RST signal line for the DS1302 RTC on the Generic Port then say Y here, otherwise leave it as N in which case the RST signal line is assumed to be connected to Port PB (just like the SCL and SDA lines). -Etrax DS1302 RST bit number +ETRAX DS1302 RST bit number CONFIG_ETRAX_DS1302_RSTBIT This is the bit number for the RST signal line of the DS1302 RTC on the selected port. If you have selected the generic port then it should be bit 27, otherwise your best bet is bit 5. -Etrax DS1302 SCL bit number +ETRAX DS1302 SCL bit number CONFIG_ETRAX_DS1302_SCLBIT This is the bit number for the SCL signal line of the DS1302 RTC on Port PB. This is probably best left at 3. -Etrax DS1302 SDA bit number +ETRAX DS1302 SDA bit number CONFIG_ETRAX_DS1302_SDABIT This is the bit number for the SDA signal line of the DS1302 RTC on Port PB. This is probably best left at 2. -Etrax 100 IDE Reset +ETRAX DS1302 Trickle charger value +CONFIG_ETRAX_DS1302_TRICKLE_CHARGE + This controls the initial value of the trickle charge register. + 0 = disabled (use this if you are unsure or have a non rechargable battery) + Otherwise the following RS and DS values can be OR:ed together to control + the charge current: + RS: 1 = 2kohm, 2 = 4kohm, 3 = 8kohm + DS: 4 = 1 diode, 8 = 2 diodes + Allowed values are (increasing current): 0, 11, 10, 9, 7, 6, 5 + +ETRAX PCF8563 Real-Time Clock driver +CONFIG_ETRAX_PCF8563 + Enables the driver for the PCF8563 Real-Time Clock battery-backed + chip on some products. + +ETRAX Real-Time Clock read only mode +CONFIG_ETRAX_RTC_READONLY + Enable this will put the RTC in read only mode. In this mode it is + not possible to change the RTC register. The RTC register value can + only be read. This should probably be disabled. + +ETRAX 100 ATA/IDE support +CONFIG_ETRAX_IDE + Enable this to get support for ATA/IDE. + You can't use parallell ports or SCSI ports + at the same time. + +ETRAX 100 IDE delay +CONFIG_ETRAX_IDE_DELAY + Number of seconds to wait for IDE drives to spin up after an IDE + reset. + +ETRAX 100 IDE Reset CONFIG_ETRAX_IDE_CSP0_8_RESET Configures the pin used to reset the IDE bus. -Etrax 100 IDE Reset +ETRAX 100 IDE Reset CONFIG_ETRAX_IDE_CSPE1_16_RESET Configures the pin used to reset the IDE bus. -Delay for drives to regain consciousness -CONFIG_ETRAX_IDE_DELAY - Sets the time to wait for disks to regain consciousness after reset. - -Etrax 100 IDE Reset +ETRAX 100 IDE Reset CONFIG_ETRAX_IDE_G27_RESET Configures the pin used to reset the IDE bus. @@ -27285,6 +27479,16 @@ This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet controller. +ETRAX 100 Ethernet slave controller +CONFIG_ETRAX_ETHERNET_LPSLAVE + This option enables a slave ETRAX 100 or ETRAX 100LX, connected to a + master ETRAX 100 or ETRAX 100LX through par0 and par1, to act as an + Ethernet controller. + +ETRAX 100 Ethernet slave controller LEDS +CONFIG_ETRAX_ETHERNET_LPSLAVE_HAS_LEDS + Enable if the slave has it's own LEDs. + ETRAX 100LX Synchronous serial ports CONFIG_ETRAX_SYNCHRONOUS_SERIAL This option enables support for the ETRAX 100LX built-in @@ -27309,11 +27513,6 @@ CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA Makes synchronous serial port 1 use DMA. -Delay for drives to regain consciousness -CONFIG_IDE_DELAY - Number of seconds to wait for IDE drives to spin up after an IDE - reset. - ARTPEC-1 support CONFIG_JULIETTE The ARTPEC-1 is a video-compression chip used in the AXIS 2100 @@ -27334,30 +27533,41 @@ for changing this is when the flash block size is bigger than 64kB (e.g. when using two parallel 16 bit flashes). -Enable Etrax100 watchdog +Enable ETRAX watchdog CONFIG_ETRAX_WATCHDOG - Enable the built-in watchdog timer support on Etrax100 embedded + Enable the built-in watchdog timer support on ETRAX embedded network computers. +ETRAX watchdog +CONFIG_ETRAX_WATCHDOG_NICE_DOGGY + By enabling this you make sure that the watchdog does not bite while + printing oopses. Recommended for development systems but not for + production releases. + +Enable reboot at out of memory +CONFIG_OOM_REBOOT + The default behaviour at out of memory is to kill processes. By + enabling this option the system will be rebooted instead. + # Choice: crisdebug Serial-0 CONFIG_ETRAX_DEBUG_PORT0 Choose a serial port for the ETRAX debug console. Default to port 0. -Etrax debug port on ser1 +ETRAX debug port on ser1 CONFIG_ETRAX_DEBUG_PORT1 Use serial port 1 for the console. -Etrax debug port on ser2 +ETRAX debug port on ser2 CONFIG_ETRAX_DEBUG_PORT2 Use serial port 2 for the console. -Etrax debug port on ser3 +ETRAX debug port on ser3 CONFIG_ETRAX_DEBUG_PORT3 Use serial port 3 for the console. -No Etrax debug port +No ETRAX debug port CONFIG_ETRAX_DEBUG_PORT_NULL Disable serial-port debugging. @@ -28193,7 +28403,7 @@ Choose this option if you have a SIS graphics card. AGP support is required for this driver to work. -Etrax Ethernet slave support (over lp0/1) +ETRAX Ethernet slave support (over lp0/1) CONFIG_ETRAX_ETHERNET_LPSLAVE This option enables a slave ETRAX 100 or ETRAX 100LX, connected to a master ETRAX 100 or ETRAX 100LX through par0 and par1, to act as an @@ -28232,12 +28442,6 @@ should normally be the mtdblock device for the partition after the last partition in the partition table. -Serial port 0 enabled -CONFIG_ETRAX_SERIAL_PORT0 - Enables the ETRAX 100 serial driver for ser0 (ttyS0) - Normally you want this on, unless you use external DMA 1 that uses - the same DMA channels. - Shutdown bit on port CSP0 CONFIG_ETRAX_SHUTDOWN_BIT Configure what pin on CSPO-port that is used for controlling power @@ -28245,7 +28449,7 @@ Software Shutdown Support CONFIG_ETRAX_SOFT_SHUTDOWN - Enable this if Etrax is used with a power-supply that can be turned + Enable this if ETRAX is used with a power-supply that can be turned off and on with PS_ON signal. Gives the possibility to detect powerbutton and then do a power off after unmounting disks. diff -Nur /home/anderstj/linux-2.4.26/Documentation/cris/README ./Documentation/cris/README --- /home/anderstj/linux-2.4.26/Documentation/cris/README 2001-05-02 01:04:56.000000000 +0200 +++ ./Documentation/cris/README 2001-06-05 14:36:26.000000000 +0200 @@ -1,6 +1,6 @@ Linux 2.4 on the CRIS architecture ================================== -$Id: README,v 1.7 2001/04/19 12:38:32 bjornw Exp $ +$Id: README,v 1.9 2001/06/05 12:36:26 bjornw Exp $ This is a port of Linux 2.4 to Axis Communications ETRAX 100LX embedded network CPU. For more information about CRIS and ETRAX please see further @@ -103,7 +103,7 @@ ETRAX 100LX 10/100MBit ethernet v2.0 (c) 2000 Axis Communications AB eth0 initialized eth0: changed MAC to 00:40:8C:CD:00:00 -ETRAX 100LX serial-driver $Revision: 1.7 $, (c) 2000 Axis Communications AB +ETRAX 100LX serial-driver $Revision: 1.9 $, (c) 2000 Axis Communications AB ttyS0 at 0xb0000060 is a builtin UART with DMA ttyS1 at 0xb0000068 is a builtin UART with DMA ttyS2 at 0xb0000070 is a builtin UART with DMA @@ -133,8 +133,7 @@ Hostname is bbox1 Telnetd starting, using port 23. using /bin/sash as shell. -sftpd[15]: sftpd $Revision: 1.7 $ starting up - +sftpd[15]: sftpd $Revision: 1.9 $ starting up And here is how some /proc entries look: @@ -181,9 +180,7 @@ -rwxr-xr-x 1 342 100 48104 Jan 01 00:00 sh -rwxr-xr-x 1 342 100 16252 Jan 01 00:00 telnetd - -(All programs are statically linked to the libc at this point - we have not ported the - shared libraries yet) +(Statically linked binaries shown) diff -Nur /home/anderstj/linux-2.4.26/Documentation/filesystems/metafiles.txt ./Documentation/filesystems/metafiles.txt --- /home/anderstj/linux-2.4.26/Documentation/filesystems/metafiles.txt 1970-01-01 01:00:00.000000000 +0100 +++ ./Documentation/filesystems/metafiles.txt 2001-09-17 13:38:43.000000000 +0200 @@ -0,0 +1,92 @@ +Metafiles +========= + +Metafiles are used to let a filesystem builder, such as mkcramfs and +mkfs.jffs2, ignore files and change attributes of files while building +the filesystem. + +This document briefly describes how Axis Communications are using metafiles +with mkcramfs amd mkfs.jffs2 and is also a proposal of a metafile standard +for filesystem builders. + + + +Metafile Format +=============== + +An instruction is a line in a metafile telling the filesystem builder if +anything special should be done with a file or directory before writing it to +the filesystem. The following instructions should be recognized by the +filesystem builder: + + +Ignore +------ +Syntax: "Ignore: FILE" + +Ignores a file or directory. I.e. FILE is not included in the filesystem. +The metafiles themselves are always ignored and do not have to be mentioned +in any metafiles. + + +IgnoreContents +-------------- +Syntax: "IgnoreContents: DIRECTORY" + +Ignores the contents of a directory. I.e. DIRECTORY is included in the +filesystem but all files and directories in DIRECTORY are ignored. + + +Include +------- +Syntax: "Include: FILE" + +Includes a file or directory. If an Include instruction is found in a +metafile, all files or directories (in the same directory as the metafile) +that are not included will be ignored (NOTE!). + + +Device +------ +Syntax: "Device: FILE TYPE MAJOR MINOR" + +Convert a regular file to a device special file. If FILE exists it will be +written to the filesystem as a character or block special file with +MAJOR and MINOR numbers. TYPE is 'b' for block and 'c' for character device. + +Example: To create the character special file /dev/ttyS0 using metafiles, +add the following line to the metafile in the /dev directory: + +Device: ttyS0 c 4 64 + + +UserId +------ +Syntax: "UserId: FILE UID" + +Change file owner. The owner of FILE will be UID. + + +DefaultUserId +------------- +Syntax: "DefaultUserId: UID" + +Change file owner recursively. All files and directories in this directory +will be owned by UID unless overridden with the UserId instruction. + + +GroupId +------- +Syntax: "GroupId: FILE GID" + +Change group ownership on a file or directory. The group membership of FILE +will be GID. + + +DefaultGroupId +-------------- +Syntax: "DefaultGroupId: UID" + +Change gruop ownership recursively. The group membership of all files and +directories in this directory will be GID unless overridden with the GroupId +instruction. diff -Nur /home/anderstj/linux-2.4.26/Makefile ./Makefile --- /home/anderstj/linux-2.4.26/Makefile 2004-04-14 15:05:41.000000000 +0200 +++ ./Makefile 2004-04-19 10:16:18.000000000 +0200 @@ -5,7 +5,7 @@ KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) -ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/) +ARCH := cris KERNELPATH=kernel-$(shell echo $(KERNELRELEASE) | sed -e "s/-//g") CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ @@ -19,7 +19,10 @@ HOSTCC = gcc HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -CROSS_COMPILE = +# Avoid having an absolute path here. Ask whichever gcc-cris was +# found in the PATH for the path to the assembler; use that directory. +# Use a simple make variable to evaluate the test once only. +CROSS_COMPILE := $(shell dirname `gcc-cris -mlinux -print-prog-name=as`)/ # # Include the make variables (CC, etc...) @@ -267,7 +270,8 @@ # 'kbuild_2_4_nostdinc :=' or -I/usr/include for kernel code and you are not UML # then your code is broken! KAO. -kbuild_2_4_nostdinc := -nostdinc -iwithprefix include +INCLUDE_PREFIX = $(shell $(CC) -print-libgcc-file-name | sed -e s/libgcc.a//) +kbuild_2_4_nostdinc := -nostdinc -iprefix $(INCLUDE_PREFIX) -iwithprefix include export kbuild_2_4_nostdinc export CPPFLAGS CFLAGS CFLAGS_KERNEL AFLAGS AFLAGS_KERNEL diff -Nur /home/anderstj/linux-2.4.26/arch/cris/.cvsignore ./arch/cris/.cvsignore --- /home/anderstj/linux-2.4.26/arch/cris/.cvsignore 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/.cvsignore 2000-11-28 14:13:39.000000000 +0100 @@ -0,0 +1 @@ +cris.ld.tmp diff -Nur /home/anderstj/linux-2.4.26/arch/cris/boot/compressed/.cvsignore ./arch/cris/boot/compressed/.cvsignore --- /home/anderstj/linux-2.4.26/arch/cris/boot/compressed/.cvsignore 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/boot/compressed/.cvsignore 2001-11-08 14:56:14.000000000 +0100 @@ -0,0 +1,2 @@ +vmlinuz +decompress.bin diff -Nur /home/anderstj/linux-2.4.26/arch/cris/boot/rescue/.cvsignore ./arch/cris/boot/rescue/.cvsignore --- /home/anderstj/linux-2.4.26/arch/cris/boot/rescue/.cvsignore 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/boot/rescue/.cvsignore 2001-01-31 16:32:09.000000000 +0100 @@ -0,0 +1,3 @@ +rescue.bin +testrescue.bin +kimagerescue.bin diff -Nur /home/anderstj/linux-2.4.26/arch/cris/config.in ./arch/cris/config.in --- /home/anderstj/linux-2.4.26/arch/cris/config.in 2004-02-18 14:36:30.000000000 +0100 +++ ./arch/cris/config.in 2004-03-29 09:22:16.000000000 +0200 @@ -26,11 +26,23 @@ comment 'General setup' bool 'Networking support' CONFIG_NET + +bool 'Support for hot-pluggable devices' CONFIG_HOTPLUG + +if [ "$CONFIG_HOTPLUG" = "y" ] ; then + source drivers/pcmcia/Config.in + source drivers/hotplug/Config.in +else + define_bool CONFIG_PCMCIA n + define_bool CONFIG_HOTPLUG_PCI n +fi + bool 'System V IPC' CONFIG_SYSVIPC bool 'BSD Process Accounting' CONFIG_BSD_PROCESS_ACCT bool 'Sysctl support' CONFIG_SYSCTL tristate 'Kernel support for ELF binaries' CONFIG_BINFMT_ELF +bool 'Select task to kill on out of memory condition' CONFIG_OOM_KILLER string 'Kernel command line' CONFIG_ETRAX_CMDLINE "root=/dev/mtdblock3" diff -Nur /home/anderstj/linux-2.4.26/arch/cris/defconfig ./arch/cris/defconfig --- /home/anderstj/linux-2.4.26/arch/cris/defconfig 2004-02-18 14:36:30.000000000 +0100 +++ ./arch/cris/defconfig 2004-02-19 15:12:57.000000000 +0100 @@ -18,6 +18,7 @@ # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_SYSCTL is not set CONFIG_BINFMT_ELF=y +CONFIG_OOM_KILLER=y # CONFIG_ETRAX_KGDB is not set # CONFIG_ETRAX_WATCHDOG is not set diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/Config.in ./arch/cris/drivers/802_11/Config.in --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/Config.in 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/Config.in 2001-05-02 18:37:11.000000000 +0200 @@ -0,0 +1,6 @@ +bool '802.11 support' CONFIG_ETRAX_802_11 y +if [ "$CONFIG_ETRAX_802_11" = "y" ]; then + choice ' 802.11 hardware driver' \ + "Rave_ext_DMA CONFIG_ETRAX_RAVE\ + PVL_mem2mem_DMA CONFIG_ETRAX_NBAND" Rave_ext_DMA +fi diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/Makefile ./arch/cris/drivers/802_11/Makefile --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/Makefile 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,54 @@ +# +# Makefile for 802.11 device drivers. +# +# +# Add new targets to obj-y (perhaps via obj-$(*)). Will be linked into +# 802_11.o. +# + +ifndef TOPDIR +TOPDIR = ../../../.. +OBJS = rave.o mib.o tx.o rx.o ioctl.o ser.o rave_global.o mem2mem.o mlme.o + +CC=gcc-cris -mlinux +CFLAGS += -I$(TOPDIR)/include -D__KERNEL__ +CFLAGS += -Wstrict-prototypes -O2 -fomit-frame-pointer -march=v10 +CFLAGS += -fno-strict-aliasing -pipe -D__linux__ +CFLAGS += -Wall # XXX: add -Werror when mlme.c cleaned up +#CFLAGS += -E + +all: $(OBJS) + +%.d: %.c + $(CC) -c -MD $(CFLAGS) $< + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(MAKECMDGOALS),patch) +-include $(OBJS:.o=.d) +endif +endif + +.PHONY: clean +clean: + rm -f *.d $(OBJS) + +endif # TOPDIR + +O_TARGET := 802_11.o + +obj-y := + +obj-$(CONFIG_ETRAX_RAVE) += rave.o mib.o tx.o rx.o ioctl.o ser.o \ + rave_global.o +obj-$(CONFIG_ETRAX_NBAND) += mem2mem.o +obj-$(CONFIG_ETRAX_802_11) += mlme.o + +include $(TOPDIR)/Rules.make + +# The patch target should be after the include +.PHONY: patch +patch: + -patch -N -F 1 $(TOPDIR)/arch/cris/drivers/Makefile cris_drivers_Makefile.patch + -patch -N -F 1 $(TOPDIR)/arch/cris/drivers/Config.in \ + cris_drivers_Config.in.patch + -patch -N -F 1 $(TOPDIR)/include/linux/wireless.h rave_wireless_h.patch diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/README ./arch/cris/drivers/802_11/README --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/README 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/README 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,25 @@ +To get started, do: 'make patch' in this directory +to patch arch/cris/drivers/Makefile and +arch/cris/drivers/Config.in to get the code in this +directory included. + + +----------------------------------------------------- + Common management code + control_types.h + mlme.c +----------------------------------------------------- +Rave Hardware driver + +rave.c +rx.c rx.h +tx.c rx.h +ioctl.c ioctl.h +mib.c mib.h +rave_global.h +----------------------------------------------------- +Memorymapped hardware driver + +hw_pvl_common.h +mem2mem.c +----------------------------------------------------- diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/compat.h ./arch/cris/drivers/802_11/compat.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/compat.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/compat.h 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,63 @@ +/*!*************************************************************************** +*! +*! FILE NAME : compat.h +*! +*! DESCRIPTION: Type declaration for different platforms. +*! +*! FUNCTIONS : None +*! (EXPORTED) +*! +*! --------------------------------------------------------------------------- +*! (C) Copyright 2001-2003, Axis Communications AB, LUND, SWEDEN +*!***************************************************************************/ + +#ifndef COMPAT_H +#define COMPAT_H + +/****************** INCLUDE FILES SECTION ***********************************/ + +/****************** CONSTANT AND MACRO SECTION ******************************/ + +#ifdef __linux__ +/* Linux has these types defined */ +#ifdef __KERNEL__ +#include +#else +#include +#include + +typedef __u8 u8; +typedef __u16 u16; +typedef __u32 u32; +#endif +#else +/* not __linux__ */ +/* Depending on platform we need some ifdef's here */ +#ifdef __CRIS__ +#define CHAR8_SHORT16_INT32 +#else +#warning "size not verified assuming char8 short16 int32" +#define CHAR8_SHORT16_INT32 +#endif + +#ifdef CHAR8_SHORT16_INT32 +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +#endif + +#endif /* not __linux__ */ + +#define ATTR_DATA __attribute__ ((section (".rxcache_data"))) +#define ATTR_ALIGNED_DATA __attribute__ ((section (".rxcache_data"),aligned(32) )) +typedef u32 word32; + + +#define __PACKED __attribute__((packed)) + +/****************** TYPE DEFINITION SECTION *********************************/ + +/****************** EXPORTED FUNCTION DECLARATION SECTION *******************/ + +#endif /* COMPAT_H */ +/****************** END OF FILE compat.h ************************************/ diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/control_types.h ./arch/cris/drivers/802_11/control_types.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/control_types.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/control_types.h 2001-05-10 12:26:24.000000000 +0200 @@ -0,0 +1,392 @@ +/*!*************************************************************************** +*! +*! FILE NAME : control_types.h +*! +*! DESCRIPTION: Control message types for management related communication +*! between 802.11 MAC and the Master. +*! (Has nothing to do with 802.11 control frames sent through +*! the air) +*! +*! FUNCTIONS : None +*! (EXPORTED) +*! +*! --------------------------------------------------------------------------- +*! HISTORY +*! +*! DATE NAME CHANGES +*! ---- ---- ------- +*! Mar 8 2001 Johan Adolfsson Initial version +*! $Log: control_types.h,v $ +*! Revision 1.2 2001/05/10 10:26:24 johana +*! Added attrid_max and attrid_mac_addr structs. +*! +*! Revision 1.1 2001/05/02 16:40:57 johana +*! Start of PVL mem2mem DMA driver and common MLME stuff. +*! Some stuff copied from doc/projects/nband/src/ and from rave.c + some new. +*! Work in progress - not complete! +*! +*! Revision 1.17 2001/04/11 11:51:50 johana +*! Split STRING type in DISPLAYSTRING and OCTETSTRING (as in the MIB) +*! and clarified the null termination usage. (Review remark 6776) +*! Changed a couple of "variables" to "attributes". +*! +*! Revision 1.16 2001/04/11 09:19:08 johana +*! Rename par_id_enum to attr_id_enum (Review remark 6773) +*! +*! Revision 1.15 2001/04/11 09:14:34 johana +*! Review changes: +*! CTRLMSG_ start from 0. +*! CTRLMSG_DEBUG messages removed, use debug attributes instead. +*! ATTRID_MACSTATE takes a MAC address to use and +*! ATTRID_dot11MACAddress is now RO and not RW. +*! +*! Revision 1.14 2001/04/10 15:27:21 johana +*! Fixed review remarks 6566-6569, 6635 by larsv: +*! * Clarified "control" +*! * Added that Master is responible to do range checking. +*! * Replaced parameter and PARID with attribute and ATTR to be more +*! SNMP like in terminology. +*! * Use only GET_REQUEST, SET_REQUEST and RESPONSE +*! * Added error codes from SNMP (RFC1905) +*! +*! Revision 1.13 2001/03/30 01:40:32 larsv +*! Added status code for bad parameter value. +*! Changed read-only error to access error. +*! Changed type for associate AP debug message. +*! +*! Revision 1.12 2001/03/27 13:26:21 johana +*! More comments on CTRLMSG_RESULT_RESPONSE +*! +*! Revision 1.11 2001/03/21 15:34:02 johana +*! Decrease CTRLMSG_MAX_VALUE_LENGTH to 64*6 +*! +*! Revision 1.10 2001/03/21 14:15:07 johana +*! Use __PACKED. +*! Change the pad field to a status field, added CTRLSTATUS enum. +*! Added RO, WO or RW in PARID names. +*! Added CTRLMSG_DEBUG_ASSOCIATE_AP. +*! Changed AddressTable and added PromiscousMode.. +*! +*! +*! --------------------------------------------------------------------------- +*! (C) Copyright 2001, Axis Communications AB, LUND, SWEDEN +*!***************************************************************************/ +/* $Id: control_types.h,v 1.2 2001/05/10 10:26:24 johana Exp $ */ + +#ifndef CONTROL_TYPES_H +#define CONTROL_TYPES_H + +/****************** INCLUDE FILES SECTION ***********************************/ +#include "compat.h" + +/****************** CONSTANT AND MACRO SECTION ******************************/ + +enum{ + CTRLMSG_MAX_VALUE_LENGTH = 64*6 /* Room for MACLIST with 64 MAC's */ +}; +#define CTRL_MSG_COMMON_SIZE 8 /* Typically sizeof(control_msg_common_type) */ +#define CTRL_MSG_TOTSIZE(p) (CTRL_MSG_COMMON_SIZE + (p)->common.length) + +/****************** TYPE DEFINITION SECTION *********************************/ + +/* + |control_msg_common | + +---------+---------+---------+---------+---------------------+ + | type | length | id | status | value | + +---------+---------+---------+---------+---------------------+ + 2 octets 2 octets 2 octets 2 octets variable length + The value of the type, length, id and status field is encoded as + a little-endian unsigned integer (LSB transmitted first). + The length field specifies the length of the variable value field in octets. + The total length of a message is 2+2+2+2+length = 8+length. + + The Id field can be used to handle if multiple messages + are sent and the response is asynchronous. + Normally the host sets the Id using a counter, a response should + always be set to the same Id as the request. + + */ + + +/* WARNING! + * DO NOT CHANGE THESE VALUES!!! + * If you MUST change any of these values, both the code on the host + * and on the slave must be rebuilt! + */ + +/* Possible values for the status field + */ +typedef enum control_msg_status_enum{ + CTRLSTATUS_OK = 0x0000, + /* Some error */ + CTRLSTATUS_ERROR = 0x0001, + /* type field is unknown */ + CTRLSTATUS_ERROR_UNKNOWN_TYPE = 0x0002, + /* ATTRID unknown in GET/SET request */ + CTRLSTATUS_ERROR_ATTRID_UNKNOWN = 0x0003, + /* SNMP Errors according to RFC1905 */ + /* Operation not allowed on ATTRID in GET/SET request */ + CTRLSTATUS_ERROR_ATTRID_NO_ACCESS = 0x0004, + /* Not allowed to modify the attribute with a SET request */ + CTRLSTATUS_ERROR_ATTRID_NOT_WRITABLE = 0x0005, + /* Invalid value for ATTRID in GET/SET request */ + CTRLSTATUS_ERROR_ATTRID_WRONG_TYPE = 0x0006, + /* Invalid length of value for ATTRID in SET request */ + CTRLSTATUS_ERROR_ATTRID_WRONG_LENGTH = 0x0007, + /* Wrong encoding of value for ATTRID in SET request */ + CTRLSTATUS_ERROR_ATTRID_WRONG_ENCODING = 0x0008, + /* Wrong value for ATTRID in SET request */ + CTRLSTATUS_ERROR_ATTRID_WRONG_VALUE = 0x0009, + /* end of SNMP Errors according to RFC1905 */ + + + CTRLSTATUS_MAX /* Last */ +} control_msg_status_enum_type; + + +/* Values for the type field */ +typedef enum control_msg_enum +{ + CTRLMSG_MIN = 0x0000, + /* Send in response to some commands to indicate if they succeeded. + * Status is enum in control_msg_response_status_enum_type + * CTRLMSG_RESULT_RESPONSE is also used to signal error when a + * received message is incomplete or corrupt. + */ +/* Get the value of an attribute. The response is a RESPONSE message */ + CTRLMSG_GET_REQUEST = 0x0000, /* val=attrid, return RESPONSE */ + +/* Set the value of an attribute. The response is a RESPONSE message */ + CTRLMSG_SET_REQUEST = 0x0001, /* val=attrid,value, return RESPONSE */ + +/* Response from a GET_REQUEST or SET_REQUEST, + * return the actual attrid and value. + * If ok, val=attrid,value is returned + * If error, val=0x0000 (ATTRID_ERROR) + */ + CTRLMSG_RESPONSE = 0x0002, /* val=attrid,value */ + + + CTRLMSG_MAX, /* The last value defined */ +}control_msg_enum_type; + + +/* Attribute Ids: + naming: ATTRIDprefix_NAME_direction_TYPEsuffix + direction: + RO = Read only from host side + WO = Write only from host side + RW = Read/write access + + TYPEsuffixes: + NOVALUE = No value, the ATTRID itself contains the info. + MAC=6 octets (transferred as a byte array highest byte first) + MACLIST = List of MACs (transferred as a list of MAC addresses ) + U16 = 16 bit integer (2 octets) (transferred as little-endian) + U32 = 32 bit integer (4 octets) (transferred as little-endian) + U32PAIR = 2 x U32 + U32PAIRLIST = List of U32PAIRs + DISPLAYSTRING = string of octets in NVT ASCII (See MIB doc) + The string should be null terminated and the length + is including the null termination. + The +1 in allowed values in comments after the + ATTRID_ below indicates the null terminator. + + OCTETSTRING = string of octets + COUNTER = same as U32 (could be U16 if we're short on space) + + The Master is responsible for doing range checking of attribute values + before they are sent to the MAC. + +*/ + +/* WARNING! + * DO NOT CHANGE THESE VALUES!!! + * If you MUST change any of these values, both the code on the host + * and on the slave must be rebuilt! + */ +/* For dot11 MIB attributes, the id is using the following bit fields: + dot11group << 12 | dot11subgroup << 8 | value + */ + + +typedef enum attr_id_enum /* 2 octets */ +{ + ATTRID_NONE = 0x0000, + ATTRID_ERROR = 0x0000, /* Same as ATTRID_NONE */ + /* --Generic non dot11 attributes 0x0001-0x00FF ------------------------ */ + /* Used to START and STOP the MAC and supply it a MAC address to use. + * When starting a MAC address should be supplied, + * when stopping the MAC chould be 000000000000 + */ + ATTRID_MACSTATE_RW_MAC = 0x0001, + + /* --Debug attributes 0x0100-0x1FF ------------------------------------- */ + /* Used during testing to skip authorisation ans association sequence before + * MAC accepts packets. + */ + ATTRID_DEBUG_ASSOCIATE_AP_WO_MAC = 0x0100, /* value is a MAC of AP */ + + /* -------------------------------------------------------------------- */ + /* dot11 1 dot11smt */ +/* We might add these some day... + dot11StationID MacAddress, + dot11MediumOccupancyLimit INTEGER, + dot11CFPollable TruthValue, + dot11CFPPeriod INTEGER, + dot11CFPMaxDuration INTEGER, + dot11AuthenticationResponseTimeOut INTEGER, + dot11PrivacyOptionImplemented TruthValue, + dot11PowerManagementMode INTEGER, + dot11DesiredSSID OCTET STRING, + dot11DesiredBSSType INTEGER, + dot11OperationalRateSet OCTET STRING, + dot11BeaconPeriod INTEGER, + dot11DTIMPeriod INTEGER, + dot11AssociationResponseTimeOut INTEGER, + dot11DisassociateReason INTEGER, + dot11DisassociateStation MacAddress, + dot11DeauthenticateReason INTEGER, + dot11DeauthenticateStation MacAddress, + dot11AuthenticateFailStatus INTEGER, + dot11AuthenticateFailStation MacAddress } + +*/ + + /* -------------------------------------------------------------------- */ + /* dot11 2 dot11mac, 1 Operation */ + ATTRID_dot11MACAddress_RO_MAC = 0x2101, + /* Not same as dot11StationID */ + + ATTRID_dot11RTSThreshold_RW_U16 = 0x2102, /* 0..2347 */ + ATTRID_dot11ShortRetryLimit_RW_U16 = 0x2103, /* 1..255 */ + ATTRID_dot11LongRetryLimit_RW_U16 = 0x2104, /* 1..255 */ + ATTRID_dot11FragmentationThreshold_RW_U16 = 0x2105, /* 256..2346 */ + ATTRID_dot11MaxTransmitMSDULifetime_RW_U32 = 0x2106, /* 1..4294967295 */ + ATTRID_dot11MaxReceveLifetime_RW_U32 = 0x2107, /* 1..4294967295 */ + ATTRID_dot11ManufacturerID_RO_DISPLAYSTRING= 0x2108, /* size 0..128+1 */ + ATTRID_dot11ProductID_RO_DISPLAYSTRING = 0x2109, /* size 0..128+1 */ + + /* dot11 2 dot11mac, 2 Counters */ + ATTRID_dot11TransmittedFragmentCount_RO_COUNTER = 0x2201, + ATTRID_dot11MulticastTransmittedFrameCount_RO_COUNTER = 0x2202, + ATTRID_dot11FailedCount_RO_COUNTER = 0x2203, + ATTRID_dot11RetryCount_RO_COUNTER = 0x2204, + ATTRID_dot11MultipleRetryCount_RO_COUNTER = 0x2205, + ATTRID_dot11FrameDuplicateCount_RO_COUNTER = 0x2206, + ATTRID_dot11RTSSuccessCount_RO_COUNTER = 0x2207, + ATTRID_dot11RTSFailureCount_RO_COUNTER = 0x2208, + ATTRID_dot11ACKFailureCount_RO_COUNTER = 0x2209, + ATTRID_dot11ReceivedFragmentCount_RO_COUNTER = 0x220A, + ATTRID_dot11MulticastReceivedFrameCount_RO_COUNTER = 0x220B, + ATTRID_dot11FCSErrorCount_RO_COUNTER = 0x220C, + ATTRID_dot11TransmittedFrameCount_RO_COUNTER = 0x220D, + ATTRID_dot11WEPUndecryptableCount_RO_COUNTER = 0x220E, + + /* dot11 2 dot11mac, 3 GroupAddresses */ + /* We have one list with the MAC's instead of dot11GroupAddressesEntry with + dot11GroupAddressesIndex Integer32, + dot11Address MacAddress, + dot11GroupAddressesStatus RowStatus + fields. + */ + /* Setting the ATTRID_XXdot11PromiscousMode_WO_NOVALUE will disable the use + * of ATTRID_XXdot11AddressTable_WO_MACLIST. + * To disable promiscous mode, set the AddressTable again. + */ + ATTRID_XXdot11AddressTable_WO_MACLIST = 0x2300, /* NOTE: not MIB compliant */ + ATTRID_XXdot11PromiscousMode_WO_NOVALUE = 0x2301, /* NOTE: not MIB compliant */ + /*dot11Address1,2,-32 and dot11Address1-32 */ + + /* -------------------------------------------------------------------- */ + /* dot11 3 dot11res */ + + /* -------------------------------------------------------------------- */ + /* dot11 4 dot11phy 1 Operation */ + /* dot11 4 dot11phy 2 Antenna */ + /* dot11 4 dot11phy 3 TxPower */ + /* dot11 4 dot11phy 4 FHSS */ + /* dot11 4 dot11phy 5 DSSS */ + /* dot11 4 dot11phy 6 IR */ + /* dot11 4 dot11phy 7 RegDomainsSupported */ + /* dot11 4 dot11phy 8 AntennasList */ + + /* dot11 4 dot11phy 9 SupportedDataRatesTx */ + /* List of pairs containing + * SupportedDataRatesTxIndex, SupportedDataRatesTxValue + */ + ATTRID_dot11SupportedDataRatesTxEntry_RO_U32PAIRLIST = 0x4900, + + + /* dot11 4 dot11phy 10 SupportedDataRatesRx */ + /* List of pairs containing + * SupportedDataRatesRxIndex, SupportedDataRatesRxValue + */ + ATTRID_dot11SupportedDataRatesRxEntry_RO_U32PAIRLIST = 0x4A00, + + + ATTRID_MAX /* Last value */ +} attr_id_type; + +#define MAC_ADDRESS_SIZE 6 +typedef u8 mac_address_type[MAC_ADDRESS_SIZE]; + + + +/**************************************** + * Data structure to pass control data + */ +typedef struct control_msg_common_struct +{ + u16 type; /* enum control_msg_type */ + u16 length; /* Length of value field */ + u16 id; /* transaction id */ + u16 status; /* enum control_msg_status_enum_type */ +}control_msg_common_type __PACKED; + +typedef struct control_msg_struct +{ + control_msg_common_type common; + u8 value[1]; /* This is really variable length */ +}control_msg_type __PACKED; + +typedef struct control_msg_max_struct +{ + control_msg_common_type common; + u8 value[CTRLMSG_MAX_VALUE_LENGTH]; +}control_msg_max_type __PACKED; + +typedef struct control_msg_attrid_max_struct +{ + control_msg_common_type common; + u16 attrid; + u8 value[CTRLMSG_MAX_VALUE_LENGTH-2]; +}control_msg_attrid_max_type __PACKED; + +typedef struct control_msg_u16_struct +{ + control_msg_common_type common; + u16 value_u16; +}control_msg_u16_type __PACKED; + + +typedef struct control_msg_attrid_val16_struct +{ + control_msg_common_type common; + u16 attrid; + u16 attrval16; +}control_msg_attrid_val16_type __PACKED; + +typedef struct control_msg_attrid_mac_addr_struct +{ + control_msg_common_type common; + u16 attrid; + mac_address_type mac_address; +}control_msg_attrid_mac_addr_type __PACKED; + + +/****************** EXPORTED FUNCTION DECLARATION SECTION *******************/ + +#endif /* CONTROL_TYPES_H */ +/****************** END OF FILE control_types.h *****************************/ + diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/cris_drivers_Config.in.patch ./arch/cris/drivers/802_11/cris_drivers_Config.in.patch --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/cris_drivers_Config.in.patch 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/cris_drivers_Config.in.patch 2001-05-02 18:35:49.000000000 +0200 @@ -0,0 +1,14 @@ +Index: Config.in +=================================================================== +RCS file: /n/cvsroot/os/linux/arch/cris/drivers/Config.in,v +retrieving revision 1.31 +diff -u -p -r1.31 Config.in +--- Config.in 2001/04/23 13:36:30 1.31 ++++ Config.in 2001/05/02 11:51:02 +@@ -176,4 +176,6 @@ if [ "$CONFIG_ETRAX_DS1302" = "y" ]; the + int ' DS1302 SDA bit number' CONFIG_ETRAX_DS1302_SDABIT 0 + fi + ++source arch/cris/drivers/802_11/Config.in ++ + endmenu diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/cris_drivers_Makefile.patch ./arch/cris/drivers/802_11/cris_drivers_Makefile.patch --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/cris_drivers_Makefile.patch 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/cris_drivers_Makefile.patch 2001-09-27 10:48:45.000000000 +0200 @@ -0,0 +1,16 @@ +Index: Makefile +=================================================================== +RCS file: /n/cvsroot/os/linux/arch/cris/drivers/Makefile,v +retrieving revision 1.18 +diff -u -r1.18 Makefile +--- Makefile 2001/06/06 08:56:24 1.18 ++++ Makefile 2001/09/27 08:30:09 +@@ -23,5 +23,8 @@ + obj-$(CONFIG_ETRAX_ETHERNET_LPSLAVE) += lpslave/lpslavedrivers.o + subdir-$(CONFIG_ETRAX_ETHERNET_LPSLAVE) += lpslave + ++obj-$(CONFIG_ETRAX_802_11) += 802_11/802_11.o ++subdir-$(CONFIG_ETRAX_802_11) += 802_11 ++ + include $(TOPDIR)/Rules.make + diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/hw_pvl_common.h ./arch/cris/drivers/802_11/hw_pvl_common.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/hw_pvl_common.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/hw_pvl_common.h 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,54 @@ +/*!*************************************************************************** +*! +*! FILE NAME : hw_pvl_common.h +*! +*! DESCRIPTION: Common things between Master and Slave PVL driver +*! +*! FUNCTIONS : +*! (EXPORTED) +*! +*! --------------------------------------------------------------------------- +*! (C) Copyright 2001-2003, Axis Communications AB, LUND, SWEDEN +*!***************************************************************************/ + +#ifndef HW_PVL_COMMON_H +#define HW_PVL_COMMON_H + +/****************** INCLUDE FILES SECTION ***********************************/ + +#include "compat.h" + +/****************** CONSTANT AND MACRO SECTION ******************************/ + +/****************** TYPE DEFINITION SECTION *********************************/ + +/* WARNING! + * DO NOT CHANGE THESE VALUES or TYPES!!! + * If you MUST change any of these values, both the code on the host + * and on the slave must be rebuilt! + */ + + +/* A PVL transfer is specified in multiples of 32 bytes, + * so this structure is 32 bytes long + * The info in this struct is used to setup a + */ +enum{ + HW_PVL_PAD_SIZE = 24 +}; + + + +typedef struct hw_pvl_control_transfer_struct +{ + u16 type; /* type of transfer (enum pkttype) */ + u16 tot_length; /* Total length of data, always a multiple of 32 bytes */ + u16 data_ofs; /* Offset to real data in datastart[] */ + u16 data_length; /* Length of real data */ + u8 pad[HW_PVL_PAD_SIZE]; /* Padding, can be used for inline control_msg */ +}hw_pvl_control_transfer_type; + +/****************** EXPORTED FUNCTION DECLARATION SECTION *******************/ + +#endif /* HW_PVL_COMMON_H */ +/****************** END OF FILE hw_pvl_common.h *****************************/ diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/ioctl.c ./arch/cris/drivers/802_11/ioctl.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/ioctl.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/ioctl.c 2001-10-17 17:10:09.000000000 +0200 @@ -0,0 +1,95 @@ +#include "mib.h" +#include + +/* 802.11 counter attribute id:s */ +static const attr_id_type dot11_counter_ids[] = +{ + ATTRID_dot11TransmittedFragmentCount_RO_COUNTER, + ATTRID_dot11MulticastTransmittedFrameCount_RO_COUNTER, + ATTRID_dot11FailedCount_RO_COUNTER, +/* dot11_counter dot11RetryCount; -- not supported */ +/* dot11_counter dot11MultipleRetryCount; -- not supported */ + ATTRID_dot11FrameDuplicateCount_RO_COUNTER, + ATTRID_dot11RTSSuccessCount_RO_COUNTER, + ATTRID_dot11RTSFailureCount_RO_COUNTER, + ATTRID_dot11ACKFailureCount_RO_COUNTER, + ATTRID_dot11ReceivedFragmentCount_RO_COUNTER, + ATTRID_dot11MulticastReceivedFrameCount_RO_COUNTER, + ATTRID_dot11FCSErrorCount_RO_COUNTER, + ATTRID_dot11TransmittedFrameCount_RO_COUNTER, + ATTRID_dot11WEPUndecryptableCount_RO_COUNTER +}; + +/* Get 802.11 counters */ +enum { + /* odd numbers for get */ + SIOCGIWCOUNT = (SIOCDEVPRIVATE & ~0x1) + 1 +}; + +/* Generic ioctl limits */ +enum { + IOCTL_GEN_START = SIOCSIWAP, + IOCTL_GEN_END = SIOCGIWRETRY +}; + +/* Map generic ioctl number to MIB attribute id */ +static const attr_id_type ioctl_mib_map[] = { + ATTRID_dot11MACAddress_RO_MAC, /* SIOCSIWAP, SIOCGIWAP */ + ATTRID_NONE, /* none, SIOCGIWAPLIST */ + ATTRID_NONE, /* none, none */ + ATTRID_NONE, /* SIOCSIWESSID, SIOCGIWESSID */ + ATTRID_NONE, /* SIOCSIWNICKN, SIOCGIWNICKN */ + ATTRID_NONE, /* none, none */ + ATTRID_NONE, /* SIOCSIWRATE, SIOCGIWRATE */ + ATTRID_dot11RTSThreshold_RW_U16, /* SIOCSIWRTS, SIOCGIWRTS */ + ATTRID_dot11FragmentationThreshold_RW_U16, /* SIOCSIWFRAG, + SIOCGIWFRAG */ + ATTRID_NONE, /* SIOCSIWTXPOW, SIOCGIWTXPOW */ + ATTRID_NONE, /* unclear how to use SIOCSIWRETRY/SIOCGIWRETRY */ +}; + +int rave_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct iwreq *iwr; + dot11_counter *counters; + + iwr = (struct iwreq *) ifr; + + /* convert ioctl number to mib attribute id and determine set/get */ + if (cmd >= IOCTL_GEN_START && cmd <= IOCTL_GEN_END) { + attr_id_type attr_id; + + rave_assert((IOCTL_GEN_START & 0x1) == 0); + attr_id = ioctl_mib_map[(cmd - IOCTL_GEN_START) / 2]; + if (IW_IS_GET(cmd)) { + return rave_mib_request(CTRLMSG_GET_REQUEST, + attr_id, + dev, + iwr); + } else { + return rave_mib_request(CTRLMSG_SET_REQUEST, + attr_id, + dev, + iwr); + } + } else if (cmd == SIOCGIWCOUNT) { + int i; + int res; + + counters = (dot11_counter *) iwr->u.data.pointer; + for (i = 0; i < sizeof(dot11_counter_ids) / + sizeof(attr_id_type); i++) { + res = rave_mib_request(CTRLMSG_GET_REQUEST, + dot11_counter_ids[i], + dev, + iwr); + if (res < 0) { + return res; + } + *(counters++) = iwr->u.nwid.value; + } + return 0; + } + /* posix compliant */ + return -ENOTTY; +} diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/ioctl.h ./arch/cris/drivers/802_11/ioctl.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/ioctl.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/ioctl.h 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,8 @@ +/* + * Ioctl Interface to the 802.11 driver + */ + +/* Device method "do_ioctl" in Linux network interface for device drivers. */ +int rave_do_ioctl(struct net_device *dev, + struct ifreq *ifr, + int cmd); diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mem2mem.c ./arch/cris/drivers/802_11/mem2mem.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mem2mem.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/mem2mem.c 2001-05-10 12:28:25.000000000 +0200 @@ -0,0 +1,604 @@ +/* $Id: mem2mem.c,v 1.2 2001/05/10 10:28:25 johana Exp $ + * + * mem2mem.c: A 802.11 driver using mem2mem DMA + * $Log: mem2mem.c,v $ + * Revision 1.2 2001/05/10 10:28:25 johana + * Added some DMA init, packet generation, using mlme_ stuff. + * Work in progress... + * + * + * Copyright (C) 2001, Axis Communictaions AB + */ + +static const char* cardname = "ETRAX 100LX 802.11 (PVL) controller Time-stamp: <2001-03-28 13:42:24 johana>"; + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include /* DMA and register descriptions */ +#include /* LED_* I/O functions */ + +#include "hw_pvl_common.h" +#include "control_types.h" + +#define ETHDEBUG +#ifdef ETHDEBUG +#define dprintk printk +#else +#define dprintk if(0) printk +#endif + +/* in mem2mem, ch7 + out mem2mem, ch6 + ch6 and ch7 collides with ser0 and extDMA1. + */ + + +/* These are bits on PA */ +#define MAC_HAS_DATA_CTRL_BIT 0 +#define MAC_HAS_DATA_DATA_BIT 0 +#define MAC_WANT_DATA_CTRL_BIT 0 +#define MAC_WANT_DATA_DATA_BIT 0 + +/* + +Init. + 1. Enable mem2mem 0. + 2. Enable dma6. + 3. Enable dma7 + 4. Set dir on PA. + 5. Enable intr on PA. + +Transmission. + 1. rave_start_xmit is called by kernel to transmit. + 2. Check MAC_WANT_DATA_CTRL bit or enable interrupt and wait + 3. Send ToMACctrl data + 4. tx_interrupt is called when transmission done. + 5. Check MAC_WANT_DATA_DATA bit or enable interrupt and wait + 6. Prepend header to packet. + 7. Append packets to DMA_OUT_CH with eop last in packet. + 8. tx_interrupt is called when transmission done. + 9. Free buffers. + +Reception. + 1. MAC_HAS_DATA_CTRL interrupt on PA + 2. Set up reception of FromMACctrl to DMA_IN_CH (mem2mem) + 3. rx_interrupt when data received + 4. Check MAC_HAS_DATA_DATA on PA or enable interrupt and wait + 5. Set up reception of FromMACdata to DMA_IN_CH (mem2mem) + 6. rx_interrupt when data received + 7. We handle packet. + + */ + +typedef enum pkttype_enum{ + PKTTYPE_MIB_DATA = 0x0000, /* control msg */ + PKTTYPE_PKT_DIX = 0x0001, /* packet in DIX format */ +} pkttype; + + + +/* Device functions */ +static int wlan_init(struct net_device *dev); +static int wlan_open(struct net_device *dev); +static int wlan_close(struct net_device *dev); +static int wlan_start_xmit (struct sk_buff *skb, struct net_device *dev); +static struct net_device_stats *wlan_get_stats(struct net_device *dev); +static int wlan_set_mac_address (struct net_device *dev, void *addr); +static void wlan_set_multicast_list (struct net_device *dev); + +/* Internal helper functions */ +static void wlan_hw_ToMAC_send_packet(char *buf, int length); + +static void wlan_hw_ToMAC_send_control_msg(control_msg_max_type *msg, + int length); + +static void wlan_hw_receive_packet(char *buf, int length); + + + +/* Interrupts */ +static void wlan_hw_GPIOA_interrupt(int irq, void *dev_id, struct pt_regs *regs); +static void wlan_hw_DMA_interrupt(int irq, void *dev_id, struct pt_regs *regs); + + + + + +/* Information that need to be kept for each board. */ +struct net_local { + struct net_device_stats stats; + + /* Tx control lock. This protects the transmit buffer ring + * state along with the "tx full" state of the driver. This + * means all netif_queue flow control actions are protected + * by this lock as well. + */ + spinlock_t lock; +}; + + +#define ALIGN32BYTE_UP(x) ( ((u32)(x)+31) & ~31) +#define ALIGN32BYTE_DOWN(x) ( ((u32)(x)) & ~31) + +static struct sk_buff *tx_skb; + +static int nolink; + + +/* When sending control_msg, we use this buffer, + * it is protected by a waitq + */ +static control_msg_max_type glob_tx_control_msg __attribute__ ((aligned(4))); + +/* Since we use mem2mem DMA there is always a Src and a Dest descriptor + * involved in each transfer. + * When sending ToMAC we must always wait for ack on PA + * after transfering ToMACctrl before we can send ToMACdata. + * When receiving FromMAC we must set up the FromMACdata descriptors + * when we know the length from FromMACctrl. + */ +static etrax_dma_descr ToMacCtrlDescSrc __attribute__ ((aligned(4))); +static etrax_dma_descr ToMacCtrlDescDest __attribute__ ((aligned(4))); +static etrax_dma_descr ToMacDataDescSrc __attribute__ ((aligned(4))); +static etrax_dma_descr ToMacDataDescDest __attribute__ ((aligned(4))); +static hw_pvl_control_transfer_type ToMACctrl __attribute__ ((aligned(4))); + + +static etrax_dma_descr FromMacCtrlDescSrc __attribute__ ((aligned(4))); +static etrax_dma_descr FromMacCtrlDescDest __attribute__ ((aligned(4))); +static etrax_dma_descr FromMacDataDescSrc __attribute__ ((aligned(4))); +static etrax_dma_descr FromMacDataDescDest __attribute__ ((aligned(4))); +static hw_pvl_control_transfer_type FromMACctrl __attribute__ ((aligned(4))); + +#if 0 +/* Fill in where the other chip is memory mapped */ +#define TO_MAC_ADDR MEM_CSP0_START +#define FROM_MAC_ADDR MEM_CSP4_START +#else +static unsigned char to_mac_addr[3000]; +static unsigned char from_mac_addr[3000]; +#define TO_MAC_ADDR to_mac_addr +#define FROM_MAC_ADDR from_mac_addr +#endif + + + +static int +wlan_init(struct net_device *dev) +{ + dprintk("\n\n######################################################################\n"); + dprintk("> mem2mem_init\n"); + dprintk("%s\n\n", cardname); + + dev->base_addr = (unsigned int)R_EXT_DMA_0_CMD; /* just to have something to show */ + + printk("%s initialized\n", dev->name); + + /* make Linux aware of the new hardware */ + + if (!dev) { + printk("dev == NULL. Should this happen?\n"); + dev = init_etherdev(dev, sizeof(struct net_local)); + } + + /* setup generic handlers and stuff in the dev struct */ + + ether_setup(dev); + + /* make room for the local structure containing stats etc */ + + dev->priv = kmalloc(sizeof(struct net_local), GFP_KERNEL); + if (dev->priv == NULL) + return -ENOMEM; + memset(dev->priv, 0, sizeof(struct net_local)); + + /* now setup our etrax specific stuff */ + + + /* Receiver DMA */ + dev->irq = MEM2MEM_DMA_RX_IRQ_NBR; + dev->dma = MEM2MEM_RX_DMA_NBR; + + /* fill in our handlers so the network layer can talk to us in the future */ + + dev->open = wlan_open; + dev->hard_start_xmit = wlan_start_xmit; + dev->stop = wlan_close; + dev->get_stats = wlan_get_stats; + dev->set_multicast_list = wlan_set_multicast_list; + dev->set_mac_address = wlan_set_mac_address; + + +#if 0 + /* set the default MAC address */ + if(wlan_set_mac_address(dev, &default_mac)) { + return -ETIMEDOUT; + } + + /* Initialise receive descriptors */ + { + int i; + int anOffset = 0; + + for(i = 0; i < NBR_OF_RX_DESC; i++) { + RxDescList[i].ctrl = 0; + RxDescList[i].sw_len = RX_DESC_BUF_SIZE; + RxDescList[i].next = virt_to_phys(&RxDescList[i + 1]); + RxDescList[i].buf = virt_to_phys(RxBuf + anOffset); + RxDescList[i].status = 0; + RxDescList[i].hw_len = 0; + anOffset += RX_DESC_BUF_SIZE; + } + + /* wrap the last one */ + i--; + RxDescList[i].ctrl = d_eol; + RxDescList[i].next = virt_to_phys(&RxDescList[0]); + } + + // print_descr(&RxDescList[0]); + // print_descr(&RxDescList[NBR_OF_RX_DESC-1]); + + /* Initialize initial pointers */ + myNextRxDesc = &RxDescList[0]; + myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; + myPrevRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; + + /* Initialize descriptor for the header we send before all + packets to the FPGA. */ + RaveHdrDesc.sw_len = sizeof(struct rave_hdr); + RaveHdrDesc.ctrl = 0; + RaveHdrDesc.buf = virt_to_phys(&rave_hdr); + RaveHdrDesc.next = virt_to_phys(&TxDesc); +#endif + + /* Initialize speed indicator stuff. */ + nolink = 0; +#if 0 + current_speed = 11; + speed_timer.expires = jiffies + NET_LINK_UP_CHECK_INTERVAL; + speed_timer.function = rave_check_speed; + add_timer(&speed_timer); + clear_led_timer.function = rave_clear_network_leds; + clear_led_timer.expires = jiffies + 10; + add_timer(&clear_led_timer); + + printk("< rave_init\n"); +#endif + return 0; +} + +static int +wlan_open(struct net_device *dev) +{ + + /* Port PA interrupt */ + if (request_irq(PA_IRQ_NBR, wlan_hw_GPIOA_interrupt, SA_SHIRQ, cardname, (void *)dev)) { + printk("PA_IRQ_NBR\n"); + goto request_fail; + } + /* Transmission DMA, needs intr to see when transmission is done. + * We only uses the RX interrupt. + */ + if (request_irq(MEM2MEM_DMA_RX_IRQ_NBR, wlan_hw_DMA_interrupt, 0, cardname, (void *)dev)) { + printk("MEM2MEM_DMA_RX_IRQ_NBR failed\n"); + goto request_fail; + } + + if (request_dma(MEM2MEM_RX_DMA_NBR, cardname)) { + printk("MEM2MEM_RX_DMA_NBR failed\n"); + goto request_fail; + } + + if (request_dma(MEM2MEM_TX_DMA_NBR, cardname)) { + printk("MEM2MEM_TX_DMA failed\n"); + + request_fail: + wlan_close(dev); + return -EACCES; + } + + /* Enable pa3 interrupt */ + *R_IRQ_MASK1_SET = + IO_STATE(R_IRQ_MASK1_SET, pa3, set); +} + +/* + The inverse routine to net_open(). + No point in changing the channels in R_GEN_CONFIG since + there is no 'unused' to set them to. + */ + +static int +wlan_close(struct net_device *dev) +{ + struct net_local *np = (struct net_local *)dev->priv; + + dprintk("Closing %s.\n", dev->name); +} + + +/* This will only be invoked if the driver is _not_ in XOFF state. + * What this means is that we need not check it, and that this + * invariant will hold if we make sure that the netif_*_queue() + * calls are done at the proper times. + */ + +static int +wlan_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct net_local *np = (struct net_local *)dev->priv; + int length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN; + unsigned char *buf = skb->data; + + dprintk("> wlan_start_xmit\n"); + + spin_lock_irq(&np->lock); /* protect from tx_interrupt */ + + tx_skb = skb; /* remember it so we can free it in the tx irq handler later */ + dev->trans_start = jiffies; + + wlan_hw_ToMAC_send_packet(buf, length); + + /* this simple TX driver has only one send-descriptor so we're full + * directly. If this had a send-ring instead, we would only do this if + * the ring got full. + */ + + netif_stop_queue(dev); + + spin_unlock_irq(&np->lock); + + dprintk("< wlan_start_xmit\n"); + return 0; +} + +/* + * Get the current statistics. + * This may be called with the card open or closed. + */ +static struct net_device_stats * +wlan_get_stats(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + printk("> wlan_get_stats\n"); + +// update_rx_stats(&lp->stats); +// update_tx_stats(&lp->stats); + + return &lp->stats; +} + +/* set MAC address of the interface. called from the core after a + * SIOCSIFADDR ioctl, and from the bootup above. + */ + +static int +wlan_set_mac_address(struct net_device *dev, void *p) +{ + struct sockaddr *addr = p; + control_msg_max_type *tx_control_msg = &glob_tx_control_msg; + + int len; + int result; + + /* remember it */ + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + dprintk("> wlan_set_mac_address, %s: changed MAC to ", dev->name); +#ifdef ETHDEBUG + { + int i; + for (i = 0; i <= 5; i++) + printk("%02X%c", dev->dev_addr[i], i!=5 ? ':' : '\n'); + } + +#endif + len = mlme_set_mac_address(tx_control_msg, dev->dev_addr); + + /* TODO: Send to MAC and wait for result */ + result = 0; + return result; + +} + +/* + * Set or clear the multicast filter for this adaptor. + * num_addrs == -1 Promiscuous mode, receive all packets + * num_addrs == 0 Normal mode, clear multicast list + * num_addrs > 0 Multicast mode, receive normal and MC packets, + * and do best-effort filtering. + */ + +static void +wlan_set_multicast_list(struct net_device *dev) +{ + int num_addr = dev->mc_count; + control_msg_max_type *tx_control_msg = &glob_tx_control_msg; + int len; + + printk("> wlan_set_multicast_list\n"); + + if (num_addr == -1) { + printk("/* promiscuous mode */\n"); + len = mlme_set_promiscous_mode(tx_control_msg); + } else if (num_addr == 0) { + printk("/* Clear the mc list */\n"); + len = mlme_set_multicast_list(tx_control_msg, num_addr, dev->mc_list); + } else { + printk("/* MC mode, receive normal and MC packets */\n"); + len = mlme_set_multicast_list(tx_control_msg, num_addr, dev->mc_list); + } +} + + +/****************************************************************************/ + +void wlan_hw_ToMAC_send_control_msg(control_msg_max_type *msg, int len) +{ + /* TODO?: Only two fields are changed in ToMACctrl, optimise it? */ + ToMACctrl.type = PKTTYPE_MIB_DATA; + ToMACctrl.data_ofs = 0; + ToMACctrl.data_length = len; + len = ALIGN32BYTE_UP(len); + ToMACctrl.tot_length = len; + + /* TODO?: Only DescSrc.buf changes so here is room for imrovments */ + ToMacCtrlDescSrc.sw_len = sizeof(hw_pvl_control_transfer_type); + ToMacCtrlDescSrc.ctrl = d_eop | d_eol | d_wait; + ToMacCtrlDescSrc.next = virt_to_phys(0); + ToMacCtrlDescSrc.buf = virt_to_phys(&ToMACctrl); + + ToMacCtrlDescDest.sw_len = sizeof(hw_pvl_control_transfer_type); + ToMacCtrlDescDest.ctrl = d_eop | d_eol | d_wait; + ToMacCtrlDescDest.next = virt_to_phys(0); + ToMacCtrlDescDest.buf = virt_to_phys(TO_MAC_ADDR); + + /* Start RX before TX */ + /* RX */ + *R_DMA_CH7_FIRST = virt_to_phys(&ToMacCtrlDescDest); + *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start); + + /* TX */ + *R_DMA_CH6_FIRST = virt_to_phys(&ToMacCtrlDescSrc); + *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start); + + /* Sending these 32 bytes takes only a few cycles, + so we wait for it to complete here */ + WAIT_DMA(MEM2MEM_TX_DMA_NBR); + WAIT_DMA(MEM2MEM_RX_DMA_NBR); + + + /* TODO?: Only DescSrc.buf and .sw_len changes so here is room for imrovments */ + ToMacDataDescSrc.sw_len = len; + ToMacDataDescSrc.ctrl = d_eop | d_eol | d_wait; + ToMacDataDescSrc.next = virt_to_phys(0); + ToMacDataDescSrc.buf = virt_to_phys(msg); + + ToMacDataDescDest.sw_len = len; + ToMacDataDescDest.ctrl = d_eop | d_eol | d_wait; + ToMacDataDescDest.next = virt_to_phys(0); + ToMacDataDescDest.buf = virt_to_phys(TO_MAC_ADDR); + + /* Start RX before TX */ + /* RX */ + *R_DMA_CH7_FIRST = virt_to_phys(&ToMacDataDescDest); + *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start); + + /* TX */ + *R_DMA_CH6_FIRST = virt_to_phys(&ToMacDataDescSrc); + *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start); + +#if 1 /* TESTING */ +/* Wait for DMA to be complete and compare contents */ + WAIT_DMA(MEM2MEM_TX_DMA_NBR); + WAIT_DMA(MEM2MEM_RX_DMA_NBR); + if (memcmp(msg, TO_MAC_ADDR, len) != 0) + { + printk("mem2mem data corrupt!\n"); + } + else + { + printk("mem2mem data %i ok\n", len); + } + +#endif + + +} + + +void +wlan_hw_ToMAC_send_packet(char *buf, int length) +{ +} + + +void +wlan_hw_receive_packet(char *buf, int length) +{ +} + + + +/****************************************************************************/ + +static void +wlan_hw_GPIOA_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *)dev_id; + unsigned long irqbits = *R_IRQ_MASK1_RD; + + dprintk("> wlan_hw_GPIO_interrupt\n"); + + if (irqbits & (1 <<(R_IRQ_MASK1_RD__pa0__BITNR+MAC_HAS_DATA_CTRL_BIT))) + { + dprintk("MAC_HAS_DATA_CTRL\n"); + } + if (irqbits & (1 <<(R_IRQ_MASK1_RD__pa0__BITNR+MAC_HAS_DATA_DATA_BIT))) + { + dprintk("MAC_HAS_DATA_DATA\n"); + } + if (irqbits & (1 <<(R_IRQ_MASK1_RD__pa0__BITNR+MAC_WANT_DATA_CTRL_BIT))) + { + dprintk("MAC_WANT_DATA_CTRL\n"); + } + if (irqbits & (1 <<(R_IRQ_MASK1_RD__pa0__BITNR+MAC_WANT_DATA_DATA_BIT))) + { + dprintk("MAC_WANT_DATA_DATA\n"); + } +} + +static void +wlan_hw_DMA_interrupt(int irq, void *dev_id, struct pt_regs * regs) +{ + struct net_device *dev = (struct net_device *)dev_id; + dprintk("> wlan_hw_DMA_interrupt\n"); +} + + + + +/****************************************************************************/ + + +static struct net_device dev_etrax_802_11; /* only got one */ +static int __init +mem2mem_init_module(void) +{ + struct net_device *d = &dev_etrax_802_11; + + printk("> mem2mem_init_module\n"); + d->init = wlan_init; + + if(register_netdev(d) == 0) + return 0; + else + return -ENODEV; +} + +module_init(mem2mem_init_module); diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mib.c ./arch/cris/drivers/802_11/mib.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mib.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/mib.c 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,373 @@ +#include "mib.h" +#include "tx.h" + +/* MAC Address */ +enum { + DOT2_MAC_ADDR_LEN = 6 +}; + +typedef struct mac_addr { + mac_address_type ddr; +} mac_addr; + +typedef u_int16_t mib_type_t; +typedef u_int16_t mib_len_t; +typedef u_int16_t mib_id_t; +typedef u_int16_t mib_stat_t; +typedef u_int16_t mib_attrid_t; + +/* Attribute Types */ +typedef enum mib_attr_type { + MIB_ATTR_TYPE_U16 = 0, + MIB_ATTR_TYPE_U32, + MIB_ATTR_TYPE_MAC, + MIB_ATTR_TYPE_GA /* group addresses */ +} mib_attr_type; + +/* Length of value for attribute different types */ +static const mib_len_t mib_attr_len[] = { 2, 4, DOT2_MAC_ADDR_LEN, 0 }; + +typedef struct mib_attr_info { + mib_attrid_t id; + mib_attr_type type; +} mib_attr_info; + +/* Attributes */ +static mib_attr_info attrs[] = { + /* dot11MacAddress */ + { ATTRID_dot11MACAddress_RO_MAC, + MIB_ATTR_TYPE_MAC, + }, + /* dot11RtsThreshold */ + { ATTRID_dot11RTSThreshold_RW_U16, + MIB_ATTR_TYPE_U16 + }, + /* dot11FragmentationThreshold */ + { ATTRID_dot11FragmentationThreshold_RW_U16, + MIB_ATTR_TYPE_U16 + }, + /* dot11TransmittedFragmentCount */ + { ATTRID_dot11TransmittedFragmentCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11MulticastTransmittedFrameCount */ + { ATTRID_dot11MulticastTransmittedFrameCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11FailedCount */ + { ATTRID_dot11FailedCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11FrameDuplicateCount */ + { ATTRID_dot11FrameDuplicateCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11RTSSuccessCount */ + { ATTRID_dot11RTSSuccessCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11RTSFailureCount */ + { ATTRID_dot11RTSFailureCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11ACKFailureCount */ + { ATTRID_dot11ACKFailureCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11ReceivedFragmentCount */ + { ATTRID_dot11ReceivedFragmentCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11MulticastReceivedFrameCount */ + { ATTRID_dot11MulticastReceivedFrameCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11FCSErrorCount */ + { ATTRID_dot11FCSErrorCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11TransmittedFrameCount */ + { ATTRID_dot11TransmittedFrameCount_RO_COUNTER, + MIB_ATTR_TYPE_U32 + }, + /* dot11WEPUndecryptableCount */ + { ATTRID_dot11WEPUndecryptableCount_RO_COUNTER, + MIB_ATTR_TYPE_U32, + }, + /* Group Address List */ + { ATTRID_XXdot11AddressTable_WO_MACLIST, + MIB_ATTR_TYPE_GA + } +}; + +typedef struct mib_msg { + mib_type_t type; + mib_len_t len; + mib_id_t id; + mib_stat_t stat; + u_int8_t value[1]; +} mib_msg __attribute__((packed)); + +typedef struct mib_req { + mib_attrid_t attrid; + union { + u_int16_t u16; + u_int32_t u32; + mac_addr mac; + u_int8_t str[1]; + } value __attribute__((packed)); +} mib_req __attribute__((packed)); + +enum { + MIB_LEN_TYPE = 2, + MIB_LEN_LEN = 2, + MIB_LEN_ID = 2, + MIB_LEN_STATUS = 2, + MIB_LEN_ATTR_ID = 2, + MIB_HDR_LEN = MIB_LEN_TYPE + MIB_LEN_LEN + MIB_LEN_ID + + MIB_LEN_STATUS, + MIB_VAL_MAX_LEN = DOT2_MAC_ADDR_LEN, + MIB_MSG_MAX_LEN = MIB_HDR_LEN + MIB_LEN_ATTR_ID + + CTRLMSG_MAX_VALUE_LENGTH +}; + +/* only support synchronous request handling for now */ +static mib_id_t cur_id = 0; +/* only support one MIB request at the time for now */ +static bool mib_pending = FALSE; +/* current receive socket buffer */ +static struct sk_buff *rx_skb = NULL; +/* wait queue for MIB requests waiting to be processed */ +static wait_queue_head_t mib_wq; +/* wait queue for MIB requests sent to slave and waiting for response */ +static wait_queue_head_t mib_sent_wq; + +/* Find information about an attribute */ +static mib_attr_info *find_attr(mib_attrid_t id); +/* Build MIB set request */ +static int build_set_req(mib_attr_type type, + attr_id_type *attr_id, + struct net_device *dev, + struct iwreq *iwr, + mib_req *req, + uint16_t *len); +/* Receive parameters in MIB message return */ +int handle_get_return(mib_attr_type type, struct iwreq *iwr, mib_req *req); +/* Send the MIB request */ +static int send_req(u_int8_t *req, u_int16_t len); +static void mib_req_enter(void); +static void mib_req_exit(void); + +void rave_mib_init(void) +{ + init_waitqueue_head(&mib_wq); + init_waitqueue_head(&mib_sent_wq); +} + +int rave_mib_request(control_msg_enum_type req_type, + attr_id_type attr_id, + struct net_device *dev, + struct iwreq *iwr) +{ + mib_attr_info *attr; + u_int16_t len; + static u_int8_t buf[MIB_MSG_MAX_LEN]; + mib_msg *msg = (mib_msg *) buf; + mib_req *req = (mib_req *) msg->value; + int res; + + /* synchronize concurrent requests */ + mib_req_enter(); + + /* find attribute */ + attr = find_attr(attr_id); + if (attr == NULL) { + res = -EINVAL; + goto done; + } + len = MIB_LEN_ATTR_ID; + + /* set value */ + if (req_type == CTRLMSG_SET_REQUEST) { + res = build_set_req(attr->type, &attr_id, dev, iwr, req, &len); + if (res < 0) { + goto done; + } + } + + /* set field values */ + msg->type = req_type; + msg->len = len; + msg->id = cur_id; + req->attrid = attr_id; + + /* send request */ + res = send_req(buf, MIB_HDR_LEN + len); + if (res < 0) { + goto done; + } + + /* block calling process until response received */ + /* XXX: handle time out somehow */ + interruptible_sleep_on(&mib_sent_wq); + + rave_assert(rx_skb != NULL); + msg = (mib_msg *) rx_skb->data; + req = (mib_req *) msg->value; + + if (msg->id != cur_id++ || msg->stat != CTRLSTATUS_OK) { + /* most likely reason for second condition, for first we would + * need errno for "internal error" */ + dev_kfree_skb_any(rx_skb); + res = -EACCES; + goto done; + } + + if (req_type == CTRLMSG_GET_REQUEST) { + res = handle_get_return(attr->type, iwr, req); + } + + done: + mib_req_exit(); + return res; +} + +void rave_mib_response(struct sk_buff *skb) +{ + rx_skb = skb; + /* wake process waiting for MIB response */ + /* XXX: a) the woken process will execute in non-interrupt-context? */ + /* b) is it ok to wake_up from here (rx interrupt context)? */ + wake_up_interruptible(&mib_sent_wq); +} + +mib_attr_info *find_attr(mib_attrid_t id) +{ + unsigned int first = 0; + unsigned int last = sizeof(attrs) / sizeof(mib_attr_info); + unsigned int mid; + + /* search for attribute id in table */ + while (1) { + mid = first + (last - first) / 2; + if (id < attrs[mid].id) { + if (mid == last) { + return NULL; + } + last = mid; + } else if (id > attrs[mid].id) { + if (mid == first) { + return NULL; + } + first = mid; + } else { + return &attrs[mid]; /* got it */ + } + } + rave_assert(0); + return NULL; +} + +int build_set_req(mib_attr_type type, + attr_id_type *attr_id, + struct net_device *dev, + struct iwreq *iwr, + mib_req *req, + uint16_t *len) +{ + *len += mib_attr_len[type]; + switch (type) { + case MIB_ATTR_TYPE_U16: + rave_assert(iwr != NULL); + req->value.u16 = iwr->u.nwid.value; + break; + case MIB_ATTR_TYPE_U32: + rave_assert(iwr != NULL); + req->value.u32 = iwr->u.nwid.value; + break; + case MIB_ATTR_TYPE_GA: + rave_assert(dev != NULL); + switch (dev->mc_count) { + case -1: + /* Promiscues mode */ + *attr_id = + ATTRID_XXdot11PromiscousMode_WO_NOVALUE; + break; + case 0: + /* empty list */ + break; + default: + { + struct dev_mc_list *mc_list = dev->mc_list; + mac_addr *addr = (mac_addr *) req->value.str; + while (mc_list != NULL) { + memcpy(addr++, mc_list->dmi_addr, + DOT2_MAC_ADDR_LEN); + *len += DOT2_MAC_ADDR_LEN; + mc_list = mc_list->next; + } + } + break; + } + break; + default: + rave_assert(0); + /* would need errno for "internal error" here */ + return -EACCES; + } + return 0; +} + +int handle_get_return(mib_attr_type type, struct iwreq *iwr, mib_req *req) +{ + rave_assert(iwr != NULL); + switch (type) { + case MIB_ATTR_TYPE_U16: + iwr->u.nwid.value = req->value.u16; + break; + case MIB_ATTR_TYPE_U32: + iwr->u.nwid.value = req->value.u32; + break; + case MIB_ATTR_TYPE_MAC: + memcpy(iwr->u.data.pointer, &req->value.mac, + DOT2_MAC_ADDR_LEN); + iwr->u.data.length = DOT2_MAC_ADDR_LEN; + break; + default: + rave_assert(0); + /* would need errno for "internal error" here */ + dev_kfree_skb_any(rx_skb); + return -EACCES; + } + return 0; +} + + +int send_req(u_int8_t *req, u_int16_t len) +{ + static struct sk_buff skb; + + skb.data = req; + skb.len = len; + + return rave_mib_start_xmit(&skb); +} + +void mib_req_enter(void) +{ + /* since this is only called from non-interrupt context, there are no + * race conditions with respect to the updating of mib_pending */ + if (mib_pending) { + /* block calling process until we are ready with pending + * request */ + interruptible_sleep_on(&mib_wq); + } + mib_pending = TRUE; +} + +void mib_req_exit(void) +{ + mib_pending = FALSE; + /* harmless to wake empty queue */ + wake_up_interruptible(&mib_wq); +} diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mib.h ./arch/cris/drivers/802_11/mib.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mib.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/mib.h 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,23 @@ +/* + * MIB Interface to the 802.11 driver + */ + +#ifndef MIB_H +#define MIB_H + +#include "rave_global.h" +#include "control_types.h" +#include +#include + +/* Initiate MIB interface */ +void rave_mib_init(void); +/* Do MIB request. Blocks caller in waitqueue until response received. */ +int rave_mib_request(control_msg_enum_type req_type, + attr_id_type attr_id, + struct net_device *dev, + struct iwreq *iwr); +/* Called by rx interrupt handler to forward response from MIB */ +void rave_mib_response(struct sk_buff *skb); + +#endif /* MIB_H */ diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mlme.c ./arch/cris/drivers/802_11/mlme.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mlme.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/mlme.c 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,142 @@ +/* + * mlme.c: MAC Layer Managment Entity code. + */ + +#include "mlme.h" +#include "control_types.h" + +enum +{ + ATTRDIR_RO, + ATTRDIR_WO, + ATTRDIR_RW +}; + +enum +{ + ATTRTYPE_NOVALUE, + ATTRTYPE_MAC, + ATTRTYPE_MACLIST, + ATTRTYPE_U16, + ATTRTYPE_U32, + ATTRTYPE_COUNTER, + ATTRTYPE_U32PAIR, + ATTRTYPE_U32PAIRLIST, + ATTRTYPE_OCTETSTRING, + ATTRTYPE_DISPLAYSTRING +}; + + +typedef struct attrdef_struct{ + u16 attrid; + const char *attrname; + u8 attrdir; + u8 attrtype; + u32 min; + u32 max; +} attrdef_struct; + + +#define ATTRDEF_MAC(name, dir, type) { ATTRID_##name##_##dir##_##type, #name, ATTRDIR_##dir, ATTRTYPE_##type, 0, 0} +#define ATTRDEF_MACLIST(name, dir, type) { ATTRID_##name##_##dir##_##type, #name, ATTRDIR_##dir, ATTRTYPE_##type, 0, 0} + +#define ATTRDEF(name, dir, type, min, max) { ATTRID_##name##_##dir##_##type, #name, ATTRDIR_##dir, ATTRTYPE_##type, min, max} + +#define ATTRDEF_INT(name, dir, type, min, max) { ATTRID_##name##_##dir##_##type, #name, ATTRDIR_##dir, ATTRTYPE_##type, min, max} + +#define ATTRDEF_DSTR(name, dir, type, min, max) { ATTRID_##name##_##dir##_##type, #name, ATTRDIR_##dir, ATTRTYPE_##type, min, max} + +#define ATTRDEF_CNT(name, dir ) { ATTRID_##name##_##dir##_COUNTER, #name, ATTRDIR_##dir, ATTRTYPE_COUNTER, 0, 0xFFFFFFFFL} + + + + +static struct attrdef_struct attrdef[] ={ + ATTRDEF_MAC(MACSTATE,RW,MAC), + ATTRDEF_MAC(DEBUG_ASSOCIATE_AP,WO,MAC), + /* dot11 2 dot11mac, 1 Operation */ + + ATTRDEF_MAC(dot11MACAddress,RO,MAC), + ATTRDEF_INT(dot11RTSThreshold,RW,U16,0,2347), + ATTRDEF_INT(dot11ShortRetryLimit,RW,U16,0,255), + ATTRDEF_INT(dot11LongRetryLimit,RW,U16,0,255), + ATTRDEF_INT(dot11FragmentationThreshold,RW,U16,256,2346), + ATTRDEF_INT(dot11MaxTransmitMSDULifetime,RW,U32,1,4294967295UL), + ATTRDEF_INT(dot11MaxReceveLifetime,RW,U32,1,4294967295UL), + ATTRDEF_DSTR(dot11ManufacturerID,RO,DISPLAYSTRING,0,128), + ATTRDEF_DSTR(dot11ProductID,RO,DISPLAYSTRING,0,128), + + /* dot11 2 dot11mac, 2 Counters */ + ATTRDEF_CNT(dot11TransmittedFragmentCount,RO), + ATTRDEF_CNT(dot11MulticastTransmittedFrameCount,RO), + ATTRDEF_CNT(dot11FailedCount,RO), + ATTRDEF_CNT(dot11RetryCount,RO), + ATTRDEF_CNT(dot11MultipleRetryCount,RO), + ATTRDEF_CNT(dot11FrameDuplicateCount,RO), + ATTRDEF_CNT(dot11RTSSuccessCount,RO), + ATTRDEF_CNT(dot11RTSFailureCount,RO), + ATTRDEF_CNT(dot11ACKFailureCount,RO), + ATTRDEF_CNT(dot11ReceivedFragmentCount,RO), + ATTRDEF_CNT(dot11MulticastReceivedFrameCount,RO), + ATTRDEF_CNT(dot11FCSErrorCount,RO), + ATTRDEF_CNT(dot11TransmittedFrameCount,RO), + ATTRDEF_CNT(dot11WEPUndecryptableCount,RO), + +/* dot11 2 dot11mac, 3 GroupAddresses */ + ATTRDEF_MACLIST(XXdot11AddressTable,WO,MACLIST), + ATTRDEF(XXdot11PromiscousMode,WO,NOVALUE, 0,0), + + /* dot11 4 dot11phy 9 SupportedDataRatesTx */ + ATTRDEF(dot11SupportedDataRatesTxEntry,RO,U32PAIRLIST,0,0), + + /* dot11 4 dot11phy 10 SupportedDataRatesRx */ + ATTRDEF(dot11SupportedDataRatesRxEntry,RO,U32PAIRLIST,0,0), +}; + +static u16 nextid = 0; + +int mlme_set_mac_address(u8 *buf, u8 *macaddr) +{ + control_msg_attrid_mac_addr_type *msg = (control_msg_attrid_mac_addr_type*)buf; + msg->common.type = CTRLMSG_SET_REQUEST; + msg->common.length = MAC_ADDRESS_SIZE; + msg->common.id = nextid++; + msg->common.status = CTRLSTATUS_OK; + msg->attrid = ATTRID_MACSTATE_RW_MAC; + memcpy(msg->mac_address, macaddr, MAC_ADDRESS_SIZE); + return CTRL_MSG_TOTSIZE(msg); +} + +int mlme_set_promiscous_mode(u8 *buf) +{ + control_msg_attrid_val16_type *msg = (control_msg_attrid_val16_type*)buf; + msg->common.type = CTRLMSG_SET_REQUEST; + msg->common.length = 2; + msg->common.id = nextid++; + msg->common.status = CTRLSTATUS_OK; + msg->attrid = ATTRID_XXdot11PromiscousMode_WO_NOVALUE; + return CTRL_MSG_TOTSIZE(msg); +} + + +int mlme_set_multicast_list(u8 *buf, int mc_count, + struct dev_mc_list *mc_list) +{ + control_msg_attrid_max_type *msg = (control_msg_attrid_max_type*)buf; + int i; + u8 *val = msg->value; + msg->common.type = CTRLMSG_SET_REQUEST; + msg->common.length = 2+MAC_ADDRESS_SIZE*mc_count; + msg->common.id = nextid++; + msg->common.status = CTRLSTATUS_OK; + msg->attrid = ATTRID_XXdot11AddressTable_WO_MACLIST; + + for (i=0; i!=mc_count; i++) { + memcpy(val, mc_list->dmi_addr, MAC_ADDRESS_SIZE); + mc_list = mc_list->next; + val += MAC_ADDRESS_SIZE; + } + + + return CTRL_MSG_TOTSIZE(msg); +} diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mlme.h ./arch/cris/drivers/802_11/mlme.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/mlme.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/mlme.h 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,15 @@ +/* + * mlme.h + */ + +#include +#include +#include "compat.h" + +/* Write mlme message to buf, return length */ +int mlme_set_mac_address(u8 *buf, u8 *macaddr); + +int mlme_set_promiscous_mode(u8 *buf); + +int mlme_set_multicast_list(u8 *buf, int mc_count, + struct dev_mc_list *mc_list); diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave.c ./arch/cris/drivers/802_11/rave.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/rave.c 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,623 @@ +/* + * rave.c: A 802.11 driver for the rave project. + */ + +/* + The name of the card. Is used for messages and in the requests for + io regions, irqs and dma channels + */ +static const char* cardname = "ETRAX 100LX 802.11 (rave) controller Time-stamp: <2001-08-30 16:05:00 ronny>"; + +/* + + in extdma0, ch5, pa3 (RX_EOP), pb0 (RX_ACK) + out extdma1, ch6 collides with ser0. + + +Init. + 1. Enable extdma 0. + 2. Enable dma5. + 3. Enable dma6 + 4. Set dir on PA and PB. + 5. Enable intr on PA. + +Transmission. + 1. rave_start_xmit is called by kernel to transmit. + 2. Prepend header to packet. + 3. Append packets to ch6 (extdma1) with eop last in packet. + 4. tx_interrupt is called when transmission done. + 5. Free buffers. + +Reception. + 1. Reception on DMA5, extdma0. + 2. FPGA interrupts on PA3 (RX_EOP), rave_rx_interrupt called. + 3. We handle packet. + 4. We ack on PB0 (RX_ACK). + + When running, configure and check like this, for example: + + cd /tmp; chmod 777 xcv_boot; chmod 777 arp; ifconfig eth1 up; ifconfig eth1 11.0.0.1 netmask 255.0.0.0 broadcast 11.255.255.255 hw ether 10:20:30:40:50:60; route add -net 11.0.0.0 netmask 255.0.0.0 eth1; ./arp -s 11.1.1.1 10:20:30:40:50:61; + + ping -c 1 11.1.1.1 + +eth0 +setenv IP 10.13.11.150 +setenv NETMASK 255.0.0.0 +setenv BROADCAST 10.255.255.255 +setenv NETWORK 10.0.0.0 +setenv GATEWAY 10.13.11.145 + +*/ + +#include "tx.h" +#include "rx.h" +#include "ser.h" +#include "ioctl.h" +#include "mib.h" + +#include +#include +#include /* DMA and register descriptions */ +#include /* LED_* I/O functions */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include /* For .config defines, checkint + the checks below for how to + config kernel */ + +#if 0 + +#ifdef CONFIG_ETRAX_DEBUG_PORT1 +#error CONFIG_ETRAX_DEBUG_PORT1 defined +#endif + +#ifndef CONFIG_ETRAX_DEBUG_PORT2 +#error CONFIG_ETRAX_DEBUG_PORT2 not defined +#endif + +#ifdef CONFIG_ETRAX_SERIAL_PORT0 +#error CONFIG_ETRAX_SERIAL_PORT0 defined +#endif + +#endif + +/* Set to 0 if you want printable control messages. */ +#if 0 + +#define START_MAC "\000" +#define START_MAC_LEN 1 + +#define STOP_MAC "\001" +#define STOP_MAC_LEN 1 + +#define SET_STATION_ADDR "\002" +#define SET_STATION_ADDR_LEN 1 + +#define MAC_OK "\000" +#define MAC_OK_LEN 1 + +#define SET_MULTICAST_LIST "\003" +#define SET_MULTICAST_LIST_LEN 1 + +/* Number of jiffies to wait for reply from MAC */ +#define SER1_TIMOUT_JIFFIES (5) + +#else + +#define SET_MULTICAST_LIST "SET_MULTICAST_LIST" +#define SET_MULTICAST_LIST_LEN (strlen("SET_MULTICAST_LIST")) + +#define SET_STATION_ADDR "SET_STATION_ADDR" +#define SET_STATION_ADDR_LEN (strlen("SET_STATION_ADDR")) + +#define START_MAC "START_MAC" +#define START_MAC_LEN (strlen("START_MAC")) + +#define STOP_MAC "STOP_MAC" +#define STOP_MAC_LEN (strlen("STOP_MAC")) + +#define MAC_OK "o" +#define MAC_OK_LEN (strlen("o")) + +/* Number of jiffies to wait for reply from MAC */ +//#define SER1_TIMOUT_JIFFIES (5) +#define SER1_TIMOUT_JIFFIES (0) + +#endif + + +/* CSP4 */ +/* XXX: move also EXT_DMA_0 initializion to rx.c */ +#define EXT_DMA0_ADDR 0xa0000000 + +/* A default ethernet address. Highlevel SW will set the real one later */ + +static struct sockaddr default_mac = { + 0, + { 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 } +}; + + +#define MAX_MEDIA_DATA_SIZE 1518 + +#define MIN_PACKET_LEN 46 + +extern etrax_dma_descr *myNextRxDesc; /* Points to the next descriptor to + to be processed */ + +#define NET_LINK_UP_CHECK_INTERVAL 200 /* 2 s */ + +/* Network speed indication. */ +#if 0 +static struct timer_list speed_timer; +static struct timer_list clear_led_timer; +static int current_speed; +#endif /* 0 */ + +int led_clear_time; +int nolink; + +/* opened device */ +static struct net_device *opened_dev = NULL; + +/* Index to functions, as function prototypes. */ + +static int rave_close (struct net_device *dev); +static int rave_open (struct net_device *dev); +static int rave_set_mac_address (struct net_device *dev, void *addr); +static int __init rave_init (struct net_device *dev); +static struct net_device_stats *rave_get_stats(struct net_device *dev); +#if 0 +static void rave_check_speed (unsigned long dummy); +static void rave_clear_network_leds (unsigned long dummy); +#endif /* 0 */ +static void rave_set_multicast_list (struct net_device *dev); + +#define tx_done(dev) (*R_DMA_CH0_CMD == 0) + +#define PA_VECTOR (11) +#define DMA_CH_5_VECTOR (21) +#define DMA_CH_6_VECTOR (22) +#define EXT_DMA0_IRQ 21 /* DMA channel 5 in R_VECT_MASK */ +#define EXT_DMA1_IRQ 22 /* DMA channel 6 in R_VECT_MASK */ + +#define DMA_IN_IRQ (EXT_DMA0_IRQ) +#define DMA_OUT_IRQ (EXT_DMA1_IRQ) +const int DMA_IN_CH=5; +const int DMA_OUT_CH=6; + + + +/* + * Check for a network adaptor of this type, and return '0' if one exists. + * If dev->base_addr == 0, probe all likely locations. + * If dev->base_addr == 1, always return failure. + * If dev->base_addr == 2, allocate space for the device and return success + * (detachable devices only). + */ + +/* init is called by kernel at startup */ + +static int __init +rave_init(struct net_device *dev) +{ + dprintk("\n\n######################################################################\n"); + dprintk("> rave_init\n"); + dprintk("%s\n\n", cardname); + + dev->base_addr = (unsigned int)R_EXT_DMA_0_CMD; /* just to have something to show */ + + printk("%s initialized\n", dev->name); + + /* make Linux aware of the new hardware */ + + if (!dev) { + printk("dev == NULL. Should this happen?\n"); + dev = init_etherdev(dev, sizeof(struct net_local)); + } + + /* setup generic handlers and stuff in the dev struct */ + + ether_setup(dev); + + /* make room for the local structure containing stats etc */ + + dev->priv = kmalloc(sizeof(struct net_local), GFP_KERNEL); + if (dev->priv == NULL) + return -ENOMEM; + memset(dev->priv, 0, sizeof(struct net_local)); + + /* now setup our etrax specific stuff */ + + /* Receiver DMA */ + dev->irq = DMA_IN_IRQ; + dev->dma = DMA_IN_CH; + + /* fill in our handlers so the network layer can talk to us in the future */ + + dev->open = rave_open; + dev->hard_start_xmit = rave_start_xmit; + dev->stop = rave_close; + dev->get_stats = rave_get_stats; + dev->do_ioctl = rave_do_ioctl; + dev->set_multicast_list = rave_set_multicast_list; + dev->set_mac_address = rave_set_mac_address; + + ser1_init(); + + /* set the default MAC address */ + if(rave_set_mac_address(dev, &default_mac)) { + return -ETIMEDOUT; + } + + rave_rx_init(); + rave_tx_init(); + rave_mib_init(); + + /* Initialize speed indicator stuff. */ + nolink = 0; +#if 0 + current_speed = 11; + speed_timer.expires = jiffies + NET_LINK_UP_CHECK_INTERVAL; + speed_timer.function = rave_check_speed; + add_timer(&speed_timer); + clear_led_timer.function = rave_clear_network_leds; + clear_led_timer.expires = jiffies + 10; + add_timer(&clear_led_timer); + + printk("< rave_init\n"); +#endif + return 0; +} + +/* + * Open/initialize the board. This is called (in the current kernel) + * sometime after booting when the 'ifconfig' program is run. + * + * This routine should set everything up anew at each open, even + * registers that "should" only need to be set once at boot, so that + * there is non-reboot way to recover if something goes wrong. + */ + +static int +rave_open(struct net_device *dev) +{ + unsigned long flags; + + dprintk("> rave_open\n"); + + /* Stop the interface while we configure it */ + *R_EXT_DMA_0_CMD = IO_STATE(R_EXT_DMA_0_CMD, run, stop); + *R_EXT_DMA_1_CMD = IO_STATE(R_EXT_DMA_1_CMD, run, stop); + + dprintk("1\n"); + + // dprintk("%8.8x %8.8x %8.8x\n", &rave_hdr.length,&rave_hdr.reserved,&rave_hdr.type); + /* Enable external DMA channels. */ + genconfig_shadow &= ~(IO_MASK(R_GEN_CONFIG, dma5) | IO_MASK(R_GEN_CONFIG, dma6)); + + *R_GEN_CONFIG = genconfig_shadow |= + (IO_STATE(R_GEN_CONFIG, dma5, extdma0) | + IO_STATE(R_GEN_CONFIG, dma6, extdma1)); + + /* clear excessive_col, over/underrun irq mask */ + /* clear dma0 and 1 eop and descr irq masks */ + + /* Reset and wait for the DMA channels */ + RESET_DMA(5); + RESET_DMA(6); + WAIT_DMA(5); + WAIT_DMA(6); + + *R_DMA_CH5_CLR_INTR = + (IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, do) | + IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, do)); + + *R_DMA_CH6_CLR_INTR = + (IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do) | + IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do)); + + dprintk("2\n"); + + /* + * Allocate IRQ first, then DMA channels and clean up in + * reverse order on failure. + */ + + + /* The following checks could be rolled into one if you want + to. If linux is correctly configured they should always + succeed. */ + + /* Port PA interrupt */ + if (request_irq(PA_VECTOR, rave_rx_interrupt, 0, cardname, (void *)dev)) { + printk("PA_VECTOR failed\n"); + goto request_fail; + } + + dprintk("3\n"); + + /* Transmission DMA, needs intr to see when transmission is done. */ + if (request_irq(DMA_CH_6_VECTOR, rave_tx_interrupt, 0, cardname, (void *)dev)) { + printk("DMA_CH_6_VECTOR failed\n"); + goto request_fail; + } + + if (request_dma(DMA_IN_CH, cardname)) { + printk("DMA_IN_CH failed\n"); + goto request_fail; + } + + if (request_dma(DMA_OUT_CH, cardname)) { + printk("DMA_OUT_CH failed\n"); + + request_fail: + rave_close(dev); + return -EACCES; + } + + dprintk("4\n"); + + + /* All the register settings should use hwregs shadow + macros. Not my fault!!!! */ + + + /* Set RX_EOP pin (pa3) to input. */ + *R_PORT_PA_DIR = port_pa_dir_shadow &= + ~(IO_STATE(R_PORT_PA_DIR, dir3, output)); + + dprintk("R_PORT_PA_DIR %8.8x\n", port_pa_dir_shadow); + + if (*R_IRQ_READ1 & IO_STATE(R_IRQ_READ1, pa3, active)) { + printk("pa3 already set, cannot enable interrupts.\n"); + goto request_fail; + } + + /* Enable pa3 interrupt. */ + *R_IRQ_MASK1_SET = + IO_STATE(R_IRQ_MASK1_SET, pa3, set); + + /* Set direction on RX_ACK pin... */ + *R_PORT_PB_DIR = port_pb_dir_shadow |= + IO_STATE(R_PORT_PB_DIR, dir0, output); + + /* ... and value. */ + *R_PORT_PB_DATA = port_pb_data_shadow &= + ~(1<priv; + + opened_dev = NULL; + dprintk("Closing %s.\n", dev->name); + + /* Stop all transmissions. */ + ser1_send(STOP_MAC, STOP_MAC_LEN); + if (ser1_expect(MAC_OK, MAC_OK_LEN, SER1_TIMOUT_JIFFIES)) { + printk("STOP_MAC failed!\n"); + } + +#ifndef ETHDEBUG + /* Don't do this if we use the debug port. */ + ser1_close(); +#endif + + *R_EXT_DMA_0_CMD = IO_STATE(R_EXT_DMA_0_CMD, run, stop); + *R_EXT_DMA_1_CMD = IO_STATE(R_EXT_DMA_1_CMD, run, stop); + + netif_stop_queue(dev); + + RESET_DMA(5); + RESET_DMA(6); + + /* Clear interrupts and masks */ + *R_DMA_CH6_CLR_INTR = + IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); + + *R_IRQ_MASK1_CLR = + IO_STATE(R_IRQ_MASK1_CLR, pa3, clr); + + *R_IRQ_MASK2_CLR = + IO_STATE(R_IRQ_MASK2_CLR, dma6_eop, clr); + + /* Free DMA channels */ + free_dma(DMA_IN_CH); + free_dma(DMA_OUT_CH); + + /* This may cause some 'trying to free free irq' but no harm done... */ + free_irq(PA_VECTOR, (void *)dev); + free_irq(DMA_CH_6_VECTOR, (void *)dev); + + /* Update the statistics */ + rave_update_rx_stats(&np->stats); + rave_update_tx_stats(&np->stats); + + rave_tx_close(); + return 0; +} + +/* Not used */ + +#if 0 +static +void rave_check_speed(unsigned long dummy) +{ + dprintk("> rave_check_speed\n"); +} +#endif /* 0 */ + +/* set MAC address of the interface. called from the core after a + * SIOCSIFADDR ioctl, and from the bootup above. + */ + +static int +rave_set_mac_address(struct net_device *dev, void *addr) +{ + /* Due to MAC address dependent states in 802.11 MAC we can't change + * MAC address online but must restart the MAC. For now, we just + * consider the operation not being permitted online. */ + if (opened_dev != NULL) { + return -EPERM; + } + /* XXX: If "open" isn't yet called, we should save the MAC address + * until it is, and then forward it in start command to slave */ + return 0; +} + +/* + * Set or clear the multicast filter for this adaptor. + * num_addrs == -1 Promiscuous mode, receive all packets + * num_addrs == 0 Normal mode, clear multicast list + * num_addrs > 0 Multicast mode, receive normal and MC packets, + * and do best-effort filtering. + */ + +static void +rave_set_multicast_list(struct net_device *dev) +{ + rave_mib_request(CTRLMSG_SET_REQUEST, + ATTRID_XXdot11AddressTable_WO_MACLIST, + dev, + NULL); +} + +/* + * Get the current statistics. + * This may be called with the card open or closed. + */ +static struct net_device_stats * +rave_get_stats(struct net_device *dev) +{ + struct net_local *lp = (struct net_local *)dev->priv; + + printk("> rave_get_stats\n"); + + rave_update_rx_stats(&lp->stats); + rave_update_tx_stats(&lp->stats); + + return &lp->stats; +} + +#if 0 +static void +rave_clear_network_leds(unsigned long dummy) +{ + + printk("> rave_clear_network_leds\n"); + + if (jiffies > led_clear_time) { + if (nolink) + ;//LED_NETWORK_TX_SET(1); + else + ;//LED_NETWORK_TX_SET(0); + //LED_NETWORK_RX_SET(0); + } + + clear_led_timer.expires = jiffies + 10; + add_timer(&clear_led_timer); +} +#endif /* 0 */ + +static struct net_device dev_etrax_rave; /* only got one */ + +void rave_failure(void) +{ +/* XXX: What to do here? */ +} + +static int +etrax_init_module(void) +{ + struct net_device *d = &dev_etrax_rave; + + dprintk("> etrax_init_module\n"); + d->init = rave_init; + + if(register_netdev(d) == 0) + return 0; + else + return -ENODEV; +} + +module_init(etrax_init_module); diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave_global.c ./arch/cris/drivers/802_11/rave_global.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave_global.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/rave_global.c 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,56 @@ +#include "rave_global.h" +#include + +void +rave_print_descr(char* buf_p) +{ + struct dma_descr { + unsigned short sw_len; /* 0-1 */ + unsigned short ctrl; /* 2-3 */ + unsigned int next; /* 4-7 */ + unsigned int buf; /* 8-11 */ + unsigned short hw_len; /* 12-13 */ + unsigned short status; /* 14-15 */ + } *dma_descr; + + printk("DMA-descriptor at: 0x%x\r\n", (unsigned)buf_p); + + dma_descr = (struct dma_descr*) buf_p; + + printk("ctrl : 0x%x : ", dma_descr->ctrl); + if (dma_descr->ctrl & 1) + printk("eol "); + if (dma_descr->ctrl & 2) + printk("eop "); + if (dma_descr->ctrl & 4) + printk("wait "); + if (dma_descr->ctrl & 8) + printk("intr "); + if (dma_descr->ctrl & 16) + printk("ecp "); + if (dma_descr->ctrl & 32) + printk("pri "); + printk("\r\n"); + + printk("sw_len : 0x%x\r\n", dma_descr->sw_len); + printk("next : 0x%8.8x\r\n", (unsigned)phys_to_virt(dma_descr->next)); + printk("buf : 0x%8.8x\r\n", (unsigned)phys_to_virt(dma_descr->buf)); + + printk("status : 0x%x : ", dma_descr->status); + if (dma_descr->status & 1) + printk("res "); + if (dma_descr->status & 2) + printk("eop "); + if (dma_descr->status & 16) + printk("stop "); + if (dma_descr->status & 32) + printk("priority "); + if (dma_descr->status & 64) + printk("align_err "); + if (dma_descr->status & 128) + printk("crc_err "); + printk("\r\n"); + + printk("hw_len : 0x%x\r\n", dma_descr->hw_len); + +} diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave_global.h ./arch/cris/drivers/802_11/rave_global.h --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave_global.h 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/rave_global.h 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,70 @@ +/* + * Global macros, typedefs and constants. + */ + +#ifndef RAVE_GLOBAL_H +#define RAVE_GLOBAL_H + +#include +#include /* for NULL only */ + +/* Guess what you can do with this? */ +#define ETHDEBUG 1 + +#ifdef ETHDEBUG +#define dprintk printk +#else +#define dprintk +#endif + +extern void rave_failure(void); + +#define rave_assert(x) \ +if (!(x)) { \ + printk("RAVE: assertion (" #x ") failed at " __FILE__ "(%d):" \ + __FUNCTION__ "\n", __LINE__); \ + rave_failure(); \ +} + +typedef char bool; + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +/* Type of packet from LLC */ +typedef enum llc_type { + LLC_TYPE_DATA = 0, + LLC_TYPE_MIB, + LLC_TYPE_INVALID +} llc_type; + +/* Interface logic header */ +typedef struct rave_header { + unsigned short length; + unsigned char reserved; + unsigned char type; +} __attribute__((packed)) rave_header; + +/* Information that need to be kept for each board. */ +typedef struct net_local { + struct net_device_stats stats; + + /* Tx control lock. This protects the transmit buffer ring + * state along with the "tx full" state of the driver. This + * means all netif_queue flow control actions are protected + * by this lock as well. + */ + spinlock_t lock; +} net_local; + + +#define RX_ACK_PIN (0) + +void rave_print_descr(char* buf_p); + +#endif /* RAVE_GLOBAL_H */ diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave_wireless_h.patch ./arch/cris/drivers/802_11/rave_wireless_h.patch --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rave_wireless_h.patch 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/rave_wireless_h.patch 2001-10-17 17:11:05.000000000 +0200 @@ -0,0 +1,51 @@ +Index: wireless.h +=================================================================== +RCS file: /n/cvsroot/os/linux/include/linux/wireless.h,v +retrieving revision 1.3 +diff -u -p -r1.3 wireless.h +--- wireless.h 2001/05/08 14:37:22 1.3 ++++ wireless.h 2001/08/09 13:29:28 +@@ -507,4 +507,43 @@ struct iw_priv_args + char name[IFNAMSIZ]; /* Name of the extension */ + }; + ++ ++/* -------------------------- MIB counters -------------------------- */ ++ ++/* ++ * Below struct is supposed to be declared in user space when 802.11 ++ * statistics is to be received via ioctl, i.e.: ++ * ++ * iwreq req; ++ * dot11Counters counters; ++ * inf fd; ++ * int res; ++ * ++ * req.union.data ++ * iwr.u.data.pointer = (caddr_t) &counters; ++ * fd = ... // open device ++ * res = ioctl(fd, SIOCGIWCOUNT, (struct ifreq *) &iwr); ++ */ ++ ++typedef __u32 dot11_counter; ++ ++/* 802.11 counters */ ++typedef struct dot11Counters ++{ ++ dot11_counter dot11TransmittedFragmentCount; ++ dot11_counter dot11MulticastTransmittedFrameCount; ++ dot11_counter dot11FailedCount; ++/* dot11_counter dot11RetryCount; -- not supported yet */ ++/* dot11_counter dot11MultipleRetryCount; -- not supported yet */ ++ dot11_counter dot11FrameDuplicateCount; ++ dot11_counter dot11RTSSuccessCount; ++ dot11_counter dot11RTSFailureCount; ++ dot11_counter dot11ACKFailureCount; ++ dot11_counter dot11ReceivedFragmentCount; ++ dot11_counter dot11MulticastReceivedFrameCount; ++ dot11_counter dot11FCSErrorCount; ++ dot11_counter dot11TransmittedFrameCount; ++ dot11_counter dot11WEPUndecryptableCount; ++} dot11Counters; ++ + #endif /* _LINUX_WIRELESS_H */ diff -Nur /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rx.c ./arch/cris/drivers/802_11/rx.c --- /home/anderstj/linux-2.4.26/arch/cris/drivers/802_11/rx.c 1970-01-01 01:00:00.000000000 +0100 +++ ./arch/cris/drivers/802_11/rx.c 2003-04-29 16:16:42.000000000 +0200 @@ -0,0 +1,316 @@ +#include "rx.h" +#include "mib.h" +#include +#include +#include + +#define RX_BUF_SIZE 32768 +/* RX_DESC_BUF_SIZE should be a multiple of four to avoid the buffer + * alignment bug in Etrax 100 release 1 + */ +#define RX_DESC_BUF_SIZE 256 +#define NBR_OF_RX_DESC (RX_BUF_SIZE / \ + RX_DESC_BUF_SIZE) + +/* Network flash constants */ +#define NET_FLASH_TIME 2 /* 20 ms */ + +#define ETHER_HEAD_LEN 14 + +static etrax_dma_descr RxDescList[NBR_OF_RX_DESC]; +unsigned char RxBuf[RX_BUF_SIZE]; +etrax_dma_descr *myNextRxDesc; /* Points to the next descriptor to + * to be processed */ +static etrax_dma_descr *myLastRxDesc; /* The last processed descriptor */ +static etrax_dma_descr *myPrevRxDesc; /* The descriptor right before + * myNextRxDesc */ +/* Network speed indication. */ +extern int led_clear_time; +extern int nolink; + +void rave_rx_init(void) +{ + int i; + int anOffset; + unsigned char *buf; + + /* Initialise receive descriptors */ + anOffset = 0; + for(i = 0; i < NBR_OF_RX_DESC; i++) { + RxDescList[i].ctrl = 0; + RxDescList[i].sw_len = RX_DESC_BUF_SIZE; + RxDescList[i].next = virt_to_phys(&RxDescList[i + 1]); + RxDescList[i].buf = virt_to_phys(RxBuf + anOffset); + RxDescList[i].status = 0; + RxDescList[i].hw_len = 0; + anOffset += RX_DESC_BUF_SIZE; + } + + /* wrap the last one */ + i--; + RxDescList[i].ctrl = d_eol; + RxDescList[i].next = virt_to_phys(&RxDescList[0]); + + memset(RxBuf, 0, RX_BUF_SIZE); + + for(i=0; i!= RX_BUF_SIZE; i++) { + RxBuf[i] = 0; + } + + buf = RxBuf; + + dprintk("%2.2x %2.2x %2.2x %2.2x %2.2x %2.2x > %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x\n", + buf[6],buf[7],buf[8],buf[9],buf[10],buf[11], + buf[0],buf[1],buf[2],buf[3],buf[4],buf[5]); + + for(i=0; i!= 500; i++) { + dprintk("%2.2x ", buf[i]); + } + + dprintk("\n"); + + /* Initialize initial pointers */ + myNextRxDesc = &RxDescList[0]; + myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; + myPrevRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; +} + +void +rave_rx_open(void) +{ +#ifdef ETHDEBUG + memset(RxBuf, 0, RX_BUF_SIZE); +#endif +} + + +/* + Called by PORT_PA interrupt. + Stop the external DMA, acknowledge on PORT_PB, send packet up higher. + RXI. +*/ +void +rave_rx_interrupt(int irq, void *dev_id, struct pt_regs * regs) +{ + struct net_device *dev = (struct net_device *)dev_id; + unsigned long irqbits = *R_IRQ_MASK1_RD; + + dprintk("> rave_rx_interrupt\n"); + +#if 0 + { + int i; + + for(i=0; i != NBR_OF_RX_DESC; i++) { + print_descr((char*)&RxDescList[i]); + } + } +#endif + + printk("\n\nR_DMA_CH5_HWSW %8.8x\n", *R_DMA_CH5_HWSW); + printk("R_DMA_CH5_FIRST %8.8x\n", *R_DMA_CH5_FIRST); + printk("R_DMA_CH5_FIRST(v) %p\n", phys_to_virt(*R_DMA_CH5_FIRST)); + printk("R_DMA_CH5_DESCR %8.8x\n", *R_DMA_CH5_DESCR); + printk("myNextRxDesc %p\n", myNextRxDesc); + + if (irqbits & IO_STATE(R_IRQ_MASK1_RD, pa3, active)) { + dprintk(" pa3 is set\n"); + + /* stop external DMA, automatically sets eop in internal + * channel */ + *R_EXT_DMA_0_CMD = (IO_STATE(R_EXT_DMA_0_CMD, cnt,disable ) | + IO_STATE(R_EXT_DMA_0_CMD, rqpol, ahigh ) | + IO_STATE(R_EXT_DMA_0_CMD, apol, ahigh ) | + IO_STATE(R_EXT_DMA_0_CMD, rq_ack, handsh ) | + IO_STATE(R_EXT_DMA_0_CMD, wid, dword ) | + IO_STATE(R_EXT_DMA_0_CMD, dir, input ) | + IO_STATE(R_EXT_DMA_0_CMD, run, stop ) | + IO_FIELD(R_EXT_DMA_0_CMD, trf_count, 0)); + + /* Wait for eop. Could do this with eop interrupt, but this + * will not take long, just waiting for the FIFO. */ + while(!(*R_IRQ_READ2 & IO_STATE(R_IRQ_READ2, dma5_eop, active))){}; + + /* check if one or more complete packets were indeed + * received */ + + while(*R_DMA_CH5_FIRST != virt_to_phys(myNextRxDesc)) { + /* Take out the buffer and give it to the OS. */ + rave_rx(dev); + ((struct net_local *)dev->priv)->stats.rx_packets++; + /* restart/continue on internal channel */ + *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, restart); + /* now, we might have gotten another packet so we + * have to loop back and check if so */ + } + + dprintk(" setting rx_ack pin\n"); + /* acknowledge the packet */ + *R_PORT_PB_DATA = port_pb_data_shadow | + 1< rave_rx\n"); + + /* blinkenlights! */ + if (!nolink) { + // LED_NETWORK_RX_SET(1); + /* Set the earliest time we may clear the LED */ + led_clear_time = jiffies + NET_FLASH_TIME; + } + + /* If the packet is broken down in many small packages then + * merge count how much space we will need to alloc with + * skb_alloc() for it to fit. + */ + while (!(myNextRxDesc->status & d_eop)) { + length += myNextRxDesc->sw_len; + // myNextRxDesc->status = 0; + myNextRxDesc = phys_to_virt(myNextRxDesc->next); + } + length += myNextRxDesc->hw_len; /* use hw_len for the last descr */ + + { + rave_hdr = (struct rave_header*)phys_to_virt(firstDesc->buf); + + printk(" Got header (%p): length %u, reserved %u, type %u\n", + rave_hdr, + rave_hdr->length, + rave_hdr->reserved, + rave_hdr->type); + } + + /* Skip the rave header, restore it later. */ + firstDesc->buf += sizeof(rave_header); + length -= sizeof(rave_header); + +#ifdef ETHDEBUG + /* dump the packet */ + skb_data_ptr = (unsigned char *)phys_to_virt(mySaveRxDesc->buf); + printk("Got a packet of length %d at 0%p:\n", length, + skb_data_ptr); + { + int i; + + for(i=0; i!= length; i++) { + if (i%8 == 0) { + printk("\n"); + } + printk("%2.2x ", skb_data_ptr[i]); + } + printk("\n"); + } +#endif + + skb = dev_alloc_skb(length - ETHER_HEAD_LEN); + if (!skb) { + printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", + dev->name); + return; + } + + skb_put(skb, length - ETHER_HEAD_LEN); /* allocate room for the packet body */ + skb_data_ptr = skb_push(skb, ETHER_HEAD_LEN); /* allocate room for the header */ + +#if 0 + printk("head = 0x%x, data = 0x%x, tail = 0x%x, end = 0x%x\n", + skb->head, skb->data, skb->tail, skb->end); + printk("copying packet to 0x%x.\n", skb_data_ptr); +#endif + + /* this loop can be made using max two memcpy's if optimized */ + while(mySaveRxDesc != myNextRxDesc) { + memcpy(skb_data_ptr, phys_to_virt(mySaveRxDesc->buf), + mySaveRxDesc->sw_len); + skb_data_ptr += mySaveRxDesc->sw_len; + mySaveRxDesc = phys_to_virt(mySaveRxDesc->next); + } + + memcpy(skb_data_ptr, phys_to_virt(mySaveRxDesc->buf), + mySaveRxDesc->hw_len); + + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + + /* Demultiplex packet by type */ + switch (rave_hdr->type) { + case LLC_TYPE_DATA: + netif_rx(skb); + break; + case LLC_TYPE_MIB: + rave_mib_response(skb); + break;