ETRAX 100LX MCM 2+8 datasheet

Table of content

• 1 MCM content
• 2 ETRAX 100LX MCM pinout
• 3 SDRAM configuration options
• 4 Implementation examples
• 4.1 SDRAM implementation examples
• 4.1 16 MByte RAM (16 bit mode), 4/6/10 MByte flash
• 4.2 16 MByte RAM (32 bit mode), 4/6/10 MByte flash
• 4.3 32 MByte RAM (32 bit mode), 4/6/10 MByte flash
• 4.2 Reset implementation
• 4.3 External Ethernet
• 5 PCB options
• 6 MCM mechanical drawings
• 7 Known problems

The ETRAX 100LX MCM is a multi chip module that contains:

#	Component	Description
1	CPU	Axis ETRAX 100LX
1	16 Mbit Flash	Atmel AT49BV161
1	64 Mbit SDRAM	Samsung K4S641632F
1	Ethernet transceiver	Broadcom 5221, FBGA
2	Reset circuit	Maxim 811S
60	Passives

Table 1

For a complete pinout description please see the ETRAX 100LX datasheet. The table below only describes the pinout differences between ETRAX 100LX and ETRAX 100LX MCM 2+8.

 

Ball	MCM Pin name	ETRAX Pin Name	Dir	Description
Ethernet / Phy
U20	phyen_	VCC	in	Active low. A low signal level on this input enables the internal Ethernet transceiver. A high signal level will put the internal Ethernet transceiver in low power mode and this will put all transceiver outputs in 3-state.
W18	rx+	NC	in	Receive pair. Differential data from the media is received on the rx+/- signal pair.
V18	rx-	NC	in
Y20	tx+	NC	out	Transmit pair. Differential data from the media is transmitted on the tx+/- signal pair.
W19	tx-	NC	out
V2	phybias	NC	-	This pin is internally connected to sensitive analog parts of the Ethernet transceiver and it is recommended that this signal be decoupled to GND. Approximately 2uF will do.
SDRAM Configuration
C16	conf0	NC	in	These pins decide how the internal SDRAM shall be configured. Either it is configured in 16-bit mode or in 32-bit mode. Please see SDRAM configuration options for further details.
B17	conf1	NC	in
A19	conf2	NC	in
B18	conf3	NC	in
D16	conf4	NC	in
SDRAM Interface
C5	csd0_	ras0_	out	These pins have exactly the same functionality as documented in ETRAX 100LX Designer's Reference.
B4	csd1_	ras1_	out
A3	sdramclk	ras2_	out
D5	cke	ras3_	out
E4	dqm0	casa0_	out
C1	dqm1	casa1_	out
D1	dqm2	casa2_	out
E2	dqm3	casa3_	out
F3	dqm4	casb0_	out
G4	dqm5	casb1_	out
F2	dqm6	casb2_	out
F1	dqm7	casb3_	out
G3	dqs	dramwe_	out
Reset
B3	mreset_	NC	in	Active low master reset input for the ETRAX 100LX MCM. A master reset signal will drive the reset output low.
Y10	reset_	reset_	out	Reset output. This reset signal is used for making a reset of the internal ETRAX 100LX and Flash chip. The same signal can be used for making a reset of external circuits as well.
Other
A16	NC	testout	out	Signal pins on ETRAX 100LX but NOT on ETRAX 100LX MCM.
U18	NC	testout2	out
Y9	NC	plllp2	out
W9	NC	pllagn	out
W10	NC	hcfg	in
V10	NC	pllvss	in

Table 2

The internal SDRAM is a 1M x 4 banks x 16 bit. This module lies in group 0 (CSD0_). If 16-bit mode is selected, no extra memory is needed but it can optionally be added in group 1 (CSD1_). If 32-bit mode is selected you need to add an additional SDRAM module on data bit 16-31 in group 0. This module must be 1M x 4 banks x 16 bit. It is important to point out that if both SDRAM groups are used, the chip configuration of the two groups must be the same. The ETRAX 100LX MCM 2+8 can have a total amount of 64 MByte RAM.

16 or 32 bit configuration is selected by connecting different address signals to the conf 0-4 pins as shown below.

	16 bit	32/64 bit
conf0	A01	A09
conf1	A09	A11
conf2	A11	A12
conf3	A12	A13
conf4	A13	A15

Table 3

The examples below describes how additional units, e.g. external memory, can be connected to the ETRAX 100LX MCM.

4.1 SDRAM implementation examples

Flash: Always 16 bit mode. Address area (CSE0_) occupied by internal 2 MByte flash.

SDRAM: Configurable 16/34/64(VMM) bit mode. 8 MByte SDRAM internally located in group0, using DQM0 and DQM1.

4.1.1 16 MByte RAM (16 bit mode), 4/6/10 MByte flash

This implementation has a total flash amount of 4, 6 or 10 MByte and 16 MByte SDRAM. Both the Flash and RAM is configured with 16 bit bus width. The address feedback to the conf0-4 inputs must be according to 16 bit mode in table 3.

R_SDRAM_CONFIG: 0x00771515
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

4.1.2 16 MByte RAM (32 bit mode), 4/6/10 MByte flash

This implementation has a total flash amount of 4, 6 or 10 MByte and 16 MByte SDRAM. The Flash is configured with 16 bit bus width and the RAM with 32 bit bus width. The address feedback to the conf0-4 inputs must be according to 32 bit mode in table 2.

R_SDRAM_CONFIG: 0x00E03636
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

4.1.3 32 MByte RAM (32 bit mode), 4/6/10 MByte flash

This implementation has a total flash amount of 4, 6 or 10 MByte and 32 MByte SDRAM. The Flash is configured with 16 bit bus width and the RAM with 32 bit bus width. The address feedback to the conf0-4 inputs must be according to 32 bit mode in table 2.

R_SDRAM_CONFIG: 0x00F83636
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

* R_SDRAM_TIMING is adjusted to the timing demands of the internal SDRAM.

4.2 Reset implementation

The ETRAX 100LX MCM contain a reset circuit that takes care of the internal reset. Thus an external reset circuit is not necessary for proper functionality but can be added if the product implementation requires it. The mreset_ input controls the internal reset circuit and can be connected as the picture shows. The reset_ output from the MCM is the same signal the makes a reset of all internal circuits, and can be used to reset external peripherals such as memory etc. The mreset_ input is active low and can be left unconnected if unused.

4.3 External Ethernet transceiver

It is possible to connect external Ethernet transceivers to the MCM module. Please note that the ETRAX 100LX MCM has only one Ethernet MAC controller. The MII interface supports multiple Ethernet transceivers connected to the same bus, only one Ethernet transceiver can be active at one time. All Ethernet transceivers must have a unique address, this is normally configured by connecting pull up/down resistors to the address inputs of the transceiver. The internal Ethernet transceiver uses address 0.
There is a control signal on the ETRAX 100LX MCM called phy_enable_ which can be used to enable/disable the internal Ethernet transceiver. A logic zero will enable and a logic one will disable the internal transceiver.

It is possible when making a PCB layout to prepare it for both ETRAX 100LX and ETRAX 100LX MCM. Since there are only a few signals that differs on the two chips this approach is quite simple. The following steps need to be done.

Ball	ETRAX 100LX MCM		ETRAX 100 LX
Ethernet / Phy
U20	phyen_	Connect to GND to enable internal phy. Connect to VCC to disable internal phy.	VCC	Connect to VCC.
W18	rx+	Ethernet transceiver input.	NC	Do not connect.
V18	rx-		NC
Y20	tx+	Ethernet transceiver output.	NC
W19	tx-		NC
V2	phybias	Connect decoupling capacitors to ground.	NC
SDRAM Configuration
C16	conf0	Connect according to Table 3.	NC	Do not connect.
B17	conf1		NC
A19	conf2		NC
B18	conf3		NC
D16	conf4		NC
Reset
B3	mreset_	Master reset input.	NC	Do not connect.
Y10	reset_	Internal reset output.	reset_	Master reset input.
Other
A16	NC	Optionally connect. Signals are not connected to internal components.	NC	Connect according to ETRAX 100LX datasheet
U18	NC		testout2
Y9	NC		plllp2
W9	NC		pllagn
W10	NC		hcfg
V10	NC		pllvss

Table 4

See these mechanical drawings for full info about footprint, etc.

See a list of known problems for ETRAX 100LX MCM 2+8.