Axis Developer Wiki

2.10_trouble_reports

Jesper Bengtsson — 2008-05-30T12:24:44+02:00

Incorrect AXIS 82 kernel configuration Problem: Incorrect MTD FLASH configuration in AXIS 82 kernelconfig-2.6 is causing the rootfs mounting to fail. Solution: Apply the patch below: --- configure-files/devboard/products/devboard_82/kernelconfig-2.6 2007-08-16 14:56:52.000000000 +0200 +++ kernelconfig-2.6 2007-08-16 15:20:20.000000000 +0200 @@ -452,17 +452,22 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -C…

axis:migrating - created

Jesper Bengtsson — 2008-04-30T12:56:14+02:00

We have gathered some information that can be useful when switching CPU in your design. * Migrating from ETRAX 100LX or ETRAX 100LX MCM 4+16 to ETRAX FS. * Migrating from ETRAX 100LX MCM 4+16 to ETRAX 100LX.

sidebar

Jesper Bengtsson — 2008-04-30T12:55:54+02:00

Axis Developer Wiki ---------- Axis Area * SDK * Compiler * Debugger * Software distribution * Download * Hardware * Migration tips * Firmware images * Feedback ---------- Public Area * FAQ * Contributions * Cookbook * Trouble reports * Tips on compiling * Links

axis:hardware

Jesper Bengtsson — 2008-04-29T16:22:07+02:00

All hardware documentation is found under the “support” tab for each product listed in the Products > System-on-Chips & Device servers section on the Axis web site. This page host additional information and tools. ETRAX FS * SDRAM calculator * [ETRAX FS errata] * For soldering recommendations, see section 24.6 in the ETRAX FS Designer's Reference. * ETRAX FS HW Design Notes

axis:hw_design_notes - created

Jesper Bengtsson — 2008-04-29T16:19:41+02:00

SDRAM clock during reset * The SDRAM needs the clock during ETRAX 100LX reset cycle to prevent the system from boot failure in case the reset occurs during an SDRAM read cycle. See the ETRAX 100LX Errata and the MCM4+16 schematics, page 3, for more details. Note The MUX workaround is already implemented in the ETRAX 100LX MCM 4+16.

axis:etrax_fs_hw_design_notes - created

Jesper Bengtsson — 2008-04-29T16:18:15+02:00

Bus arbitration signals * The brin-signal shall be connected to GND and bg-signal shall have a pull up resistor. If not, the startup can be unreliable. For more information see section “4.3.12 Bus arbitration interface” in the ETRAF FS Designer's Reference.

axis:migrate_lx_to_fs - created

Jesper Bengtsson — 2008-04-29T16:17:17+02:00

Hardware * Q: Is the 100lx and fs pin compatible. A: No, they are not. You will have to redesign your schematic and your PCB. For details, see the ETRAX FS Designer's Reference and the ETRAX 100LX Designer’s Reference. * Q: What are the main differences? A: See table below.

axis:migrate_mcm_to_lx

Jesper Bengtsson — 2008-04-25T13:11:04+02:00

It is fairly straightforward to make a design using ETRAX 100LX which is very similar to the ETRAX 100LX MCM4+16 and requiring very small software changes, at most SDRAM config registers. Even this change can be eliminated if necessary. If it's acceptable to change the SDRAM configuration in your software you can look at the design example [axis_100lx_example.pdf]. It includes the relevant parts from an Axis print server design. You can also find some important CAD guidelines on page 7 (4).

axis:serial_console

Jesper Bengtsson — 2008-03-07T10:03:49+02:00

Introduction Connecting a serial console to the target debug-port is very useful. * The target kernel and system bootup messages are displayed on the serial console. * A shell where root is logged in is opened on the debug port. This can be very useful in many cases, e.g. when developing and debugging drivers and applications.

phyter_dp83848_interfacing

habib bouaziz-viallet — 2008-02-12T08:37:30+02:00

Because we have been some difficulties to purchase Teridian Phy ethernet chip on small quantities, we decided to interface the ETRAX100LX with the low-cost Phyter DP83848 chip from NS. Schematics

sta013

habib bouaziz-viallet — 2008-02-12T08:36:07+02:00

This article shows how to interface DSP STA013 with the synchronous serial port (/dev/syncser1) of the ETRAX100LX (devboard_lx). * Linux kernel 2.4.31 * SDK 2.01 kernelconfig # # Hardware setup # .... CONFIG_ETRAX_DEF_R_PORT_PA_DIR=0xff CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0xf0 CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=0x00 CONFIG_ETRAX_DEF_R_PORT_PB_DIR=0x1e CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3 ... # # Drivers for ETRAX 100LX built-in interfaces # ... # CONFIG_ETRAX_SERIAL_PORT1 is not set # CONFIG_…

dsp_vs1002_interfacing

habib bouaziz-viallet — 2008-02-12T08:34:41+02:00

DSP VS1002 Interfacing Only 5 signals are required to control the DSP VS1002. * Legacy SPI signals i.e. CLK, DI, DO, CS for data transmission, * DREQ signal for frame flow control from DSP VS1002, * an extra signal xCS for control DSP VS1002 functions and read various status.

axis:flash_howto

Jesper Bengtsson — 2008-01-31T08:57:45+02:00

Introduction This guide describes how to flash an ETRAX based product using the most commonly used methods of flashing, all using an Ethernet network. The methods described in this document can be divided into two groups. One low level group containing methods suitable for development and production. And one high level group suitable for firmware upgrade of products on the field. The low level group comprise the “Network boot mode” method while the high level group comprise FTP and HTTP upg…